| swissChili | d813792 | 2021-02-17 15:34:07 -0800 | [diff] [blame] | 1 | [bits 32] |
| 2 | [global idt_flush] |
| 3 | |
| 4 | idt_flush: |
| 5 | mov eax, [esp + 4] |
| 6 | lidt [eax] |
| 7 | ret |
| 8 | |
| 9 | %macro ISRNOERR 1 |
| 10 | [global isr%1] |
| 11 | isr%1: |
| 12 | cli |
| swissChili | 825d46b | 2021-02-21 10:14:16 -0800 | [diff] [blame] | 13 | push 0 |
| 14 | push %1 |
| swissChili | d813792 | 2021-02-17 15:34:07 -0800 | [diff] [blame] | 15 | jmp isr_common |
| 16 | %endmacro |
| 17 | |
| 18 | %macro ISRERR 1 |
| 19 | [global isr%1] |
| 20 | isr%1: |
| 21 | cli |
| 22 | push byte %1 |
| 23 | jmp isr_common |
| 24 | %endmacro |
| 25 | |
| 26 | ISRNOERR 0 |
| 27 | ISRNOERR 1 |
| 28 | ISRNOERR 2 |
| 29 | ISRNOERR 3 |
| 30 | ISRNOERR 4 |
| 31 | ISRNOERR 5 |
| 32 | ISRNOERR 6 |
| 33 | ISRNOERR 7 |
| 34 | ISRERR 8 |
| 35 | ISRNOERR 9 |
| 36 | ISRERR 10 |
| 37 | ISRERR 11 |
| 38 | ISRERR 12 |
| 39 | ISRERR 13 |
| 40 | ISRERR 14 |
| 41 | ISRNOERR 15 |
| 42 | ISRNOERR 16 |
| 43 | ISRNOERR 17 |
| 44 | ISRNOERR 18 |
| 45 | ISRNOERR 19 |
| 46 | ISRNOERR 20 |
| 47 | ISRNOERR 21 |
| 48 | ISRNOERR 22 |
| 49 | ISRNOERR 23 |
| 50 | ISRNOERR 24 |
| 51 | ISRNOERR 25 |
| 52 | ISRNOERR 26 |
| 53 | ISRNOERR 27 |
| 54 | ISRNOERR 28 |
| 55 | ISRNOERR 29 |
| 56 | ISRNOERR 30 |
| 57 | ISRNOERR 31 |
| 58 | |
| swissChili | ee6d10d | 2021-05-29 18:05:16 -0700 | [diff] [blame] | 59 | ISRNOERR 128 |
| 60 | ISRNOERR 129 |
| swissChili | d813792 | 2021-02-17 15:34:07 -0800 | [diff] [blame] | 61 | |
| 62 | [extern isr_handler] |
| 63 | isr_common: |
| swissChili | 1e8b756 | 2021-12-22 21:22:57 -0800 | [diff] [blame^] | 64 | pushad ; Save all registers |
| swissChili | d813792 | 2021-02-17 15:34:07 -0800 | [diff] [blame] | 65 | |
| swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame] | 66 | mov ax, ds ; Save data segment |
| swissChili | d813792 | 2021-02-17 15:34:07 -0800 | [diff] [blame] | 67 | push eax |
| 68 | |
| swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame] | 69 | mov ax, 0x10 ; New segments |
| swissChili | d813792 | 2021-02-17 15:34:07 -0800 | [diff] [blame] | 70 | mov ds, ax |
| 71 | mov es, ax |
| 72 | mov fs, ax |
| 73 | mov gs, ax |
| 74 | |
| 75 | call isr_handler |
| 76 | |
| swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame] | 77 | pop eax ; Reset segments |
| swissChili | d813792 | 2021-02-17 15:34:07 -0800 | [diff] [blame] | 78 | mov ds, ax |
| 79 | mov es, ax |
| 80 | mov fs, ax |
| 81 | mov gs, ax |
| 82 | |
| swissChili | 1e8b756 | 2021-12-22 21:22:57 -0800 | [diff] [blame^] | 83 | popad |
| swissChili | d813792 | 2021-02-17 15:34:07 -0800 | [diff] [blame] | 84 | add esp, 8 ; Passed arguments |
| 85 | sti |
| 86 | iret ; Return from interrupt |