swissChili | 9b3584b | 2021-02-18 13:57:27 -0800 | [diff] [blame] | 1 | #include "pic.h" |
| 2 | #include "io.h" |
swissChili | 825d46b | 2021-02-21 10:14:16 -0800 | [diff] [blame] | 3 | #include "log.h" |
swissChili | 9b3584b | 2021-02-18 13:57:27 -0800 | [diff] [blame] | 4 | |
swissChili | 825d46b | 2021-02-21 10:14:16 -0800 | [diff] [blame] | 5 | #define ICW1_ICW4 0x01 /* ICW4 (not) needed */ |
| 6 | #define ICW1_SINGLE 0x02 /* Single (cascade) mode */ |
| 7 | #define ICW1_INTERVAL4 0x04 /* Call address interval 4 (8) */ |
| 8 | #define ICW1_LEVEL 0x08 /* Level triggered (edge) mode */ |
| 9 | #define ICW1_INIT 0x10 /* Initialization - required! */ |
swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame] | 10 | |
swissChili | 825d46b | 2021-02-21 10:14:16 -0800 | [diff] [blame] | 11 | #define ICW4_8086 0x01 /* 8086/88 (MCS-80/85) mode */ |
| 12 | #define ICW4_AUTO 0x02 /* Auto (normal) EOI */ |
| 13 | #define ICW4_BUF_SLAVE 0x08 /* Buffered mode/slave */ |
| 14 | #define ICW4_BUF_MASTER 0x0C /* Buffered mode/master */ |
| 15 | #define ICW4_SFNM 0x10 /* Special fully nested (not) */ |
swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame] | 16 | |
swissChili | aed6ff3 | 2021-05-29 17:51:04 -0700 | [diff] [blame] | 17 | typedef void (*interrupt_handler_t)(struct registers *); |
| 18 | |
| 19 | static interrupt_handler_t interrupt_handlers[256]; |
swissChili | 9b3584b | 2021-02-18 13:57:27 -0800 | [diff] [blame] | 20 | |
| 21 | void pic_send_eoi(uchar interrupt) |
| 22 | { |
swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame] | 23 | if (interrupt >= IRQ_TO_INT(8)) |
swissChili | 9b3584b | 2021-02-18 13:57:27 -0800 | [diff] [blame] | 24 | outb(PIC2_COMMAND, PIC_EOI); |
swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame] | 25 | |
swissChili | 9b3584b | 2021-02-18 13:57:27 -0800 | [diff] [blame] | 26 | outb(PIC1_COMMAND, PIC_EOI); |
| 27 | } |
| 28 | |
| 29 | void irq_handler(struct registers regs) |
| 30 | { |
| 31 | pic_send_eoi(regs.interrupt_number); |
| 32 | |
| 33 | if (interrupt_handlers[regs.interrupt_number]) |
swissChili | 825d46b | 2021-02-21 10:14:16 -0800 | [diff] [blame] | 34 | interrupt_handlers[regs.interrupt_number](®s); |
| 35 | else |
| 36 | kprintf("Unhandled hardware interrupt: %d, called from %d\n", regs.interrupt_number, regs.eip); |
swissChili | 9b3584b | 2021-02-18 13:57:27 -0800 | [diff] [blame] | 37 | } |
| 38 | |
swissChili | 825d46b | 2021-02-21 10:14:16 -0800 | [diff] [blame] | 39 | void isr_handler(struct registers regs) |
| 40 | { |
| 41 | if (interrupt_handlers[regs.interrupt_number]) |
| 42 | interrupt_handlers[regs.interrupt_number](®s); |
| 43 | else |
| 44 | kprintf("Unhandled interrupt: %d, called from %d\n", regs.interrupt_number, regs.eip); |
| 45 | } |
| 46 | |
| 47 | void add_interrupt_handler(uchar interrupt, void (*handler)(struct registers *)) |
swissChili | 9b3584b | 2021-02-18 13:57:27 -0800 | [diff] [blame] | 48 | { |
| 49 | interrupt_handlers[interrupt] = handler; |
| 50 | } |
swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame] | 51 | |
| 52 | void pic_remap() |
| 53 | { |
swissChili | 825d46b | 2021-02-21 10:14:16 -0800 | [diff] [blame] | 54 | outb(0x20, 0x11); |
| 55 | outb(0xA0, 0x11); |
| 56 | outb(0x21, 0x20); |
| 57 | outb(0xA1, 0x28); |
| 58 | outb(0x21, 0x04); |
| 59 | outb(0xA1, 0x02); |
| 60 | outb(0x21, 0x01); |
| 61 | outb(0xA1, 0x01); |
| 62 | outb(0x21, 0x0); |
| 63 | outb(0xA1, 0x0); |
swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame] | 64 | |
swissChili | aed6ff3 | 2021-05-29 17:51:04 -0700 | [diff] [blame] | 65 | memset(interrupt_handlers, 0, sizeof(interrupt_handlers)); |
swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame] | 66 | } |