| swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame] | 1 | #include "timer.h" |
| swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame] | 2 | #include "io.h" |
| swissChili | 825d46b | 2021-02-21 10:14:16 -0800 | [diff] [blame] | 3 | #include "log.h" |
| 4 | #include "pic.h" | ||||
| 5 | #include "registers.h" | ||||
| swissChili | ef97c26 | 2021-04-04 10:20:21 -0700 | [diff] [blame] | 6 | #include "task.h" |
| swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame] | 7 | |
| 8 | static ulong tick = 0; | ||||
| 9 | |||||
| swissChili | 19ef418 | 2021-02-21 17:45:51 -0800 | [diff] [blame] | 10 | static void timer_cb(struct registers *regs) |
| swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame] | 11 | { |
| swissChili | aed6ff3 | 2021-05-29 17:51:04 -0700 | [diff] [blame] | 12 | if (tasks_initialized) |
| 13 | { | ||||
| 14 | // Preemptive multitasking! | ||||
| swissChili | 1e8b756 | 2021-12-22 21:22:57 -0800 | [diff] [blame] | 15 | switch_task(*regs); |
| swissChili | aed6ff3 | 2021-05-29 17:51:04 -0700 | [diff] [blame] | 16 | } |
| swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame] | 17 | } |
| 18 | |||||
| 19 | void init_timer(uint hz) | ||||
| 20 | { | ||||
| 21 | add_interrupt_handler(IRQ_TO_INT(0), timer_cb); | ||||
| 22 | |||||
| 23 | uint divisor = TIMER_FREQ / hz; | ||||
| 24 | |||||
| swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame] | 25 | outb(0x43, 0x36); |
| swissChili | 825d46b | 2021-02-21 10:14:16 -0800 | [diff] [blame] | 26 | uchar l = divisor & 0xff, h = (divisor >> 8) & 0xff; |
| swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame] | 27 | |
| 28 | outb(0x40, l); | ||||
| swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame] | 29 | outb(0x40, h); |
| swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame] | 30 | } |