swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 1 | #include "cpu.h" |
| 2 | #include "instructions.h" |
| 3 | |
| 4 | #include <endian.h> |
| 5 | #include <stdio.h> |
| 6 | #include <stdlib.h> |
| 7 | #include <string.h> |
| 8 | |
| 9 | #define die(m, ...) \ |
swissChili | 6264a3b | 2020-07-30 19:02:07 -0700 | [diff] [blame] | 10 | printf("\033[31m" m "\033[0m\n", ##__VA_ARGS__); \ |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 11 | exit(1); |
| 12 | |
swissChili | 6264a3b | 2020-07-30 19:02:07 -0700 | [diff] [blame] | 13 | #define warn(m, ...) \ |
| 14 | printf("\033[33m" m "\033[0m\n", ##__VA_ARGS__); |
| 15 | |
swissChili | dbbd540 | 2020-08-07 15:07:39 -0700 | [diff] [blame^] | 16 | void reset(cpu_t *cpu) |
| 17 | { |
| 18 | cpu->regs[SP] = 0xFD; // stack at is 0x100 + SP |
| 19 | cpu->pc = 0; // arbitrary program counter start |
| 20 | cpu->running = true; |
| 21 | } |
| 22 | |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 23 | cpu_t new_cpu() |
| 24 | { |
| 25 | cpu_t cpu = { 0 }; |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 26 | cpu.regs[SP] = 0xFD; // stack at is 0x100 + SP |
| 27 | cpu.pc = 0; // arbitrary program counter start |
swissChili | 6264a3b | 2020-07-30 19:02:07 -0700 | [diff] [blame] | 28 | cpu.running = true; |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 29 | cpu.mem = malloc(0xFFFF); |
| 30 | memset(cpu.mem, 0, 0xFFFF); |
| 31 | |
| 32 | if (!cpu.mem) |
| 33 | { |
| 34 | die("Could not allocate memory for CPU"); |
| 35 | } |
| 36 | |
| 37 | return cpu; |
| 38 | } |
| 39 | |
swissChili | da4803e | 2020-08-06 20:06:04 -0700 | [diff] [blame] | 40 | uint16_t le_to_native(uint8_t a, uint8_t b) |
| 41 | { |
| 42 | #ifdef LITTLE_ENDIAN |
| 43 | return b << 8 | a; |
| 44 | #else |
| 45 | return a << 8 | b; |
| 46 | #endif |
| 47 | } |
| 48 | |
| 49 | void native_to_le(uint16_t n, uint8_t *a, uint8_t *b) |
| 50 | { |
| 51 | #ifdef LITTLE_ENDIAN |
| 52 | *a = n >> 8; |
| 53 | *b = n & 0xFF; |
| 54 | #else |
| 55 | *a = n & 0xFF; |
| 56 | *b = n >> 8; |
| 57 | #endif |
| 58 | } |
| 59 | |
swissChili | 6264a3b | 2020-07-30 19:02:07 -0700 | [diff] [blame] | 60 | void stack_push(cpu_t *cpu, uint8_t v) |
| 61 | { |
| 62 | cpu->mem[cpu->regs[SP]-- + 0x100] = v; |
| 63 | } |
| 64 | |
swissChili | da4803e | 2020-08-06 20:06:04 -0700 | [diff] [blame] | 65 | void stack_pushle(cpu_t *cpu, uint16_t v) |
| 66 | { |
| 67 | uint8_t a, b; |
| 68 | native_to_le(v, &a, &b); |
| 69 | // push in "reverse" order so that the address is stored as LE |
| 70 | stack_push(cpu, b); |
| 71 | stack_push(cpu, a); |
| 72 | } |
| 73 | |
swissChili | 6264a3b | 2020-07-30 19:02:07 -0700 | [diff] [blame] | 74 | uint8_t stack_pop(cpu_t *cpu) |
| 75 | { |
| 76 | return cpu->mem[cpu->regs[SP]++ + 0x100]; |
| 77 | } |
| 78 | |
swissChili | da4803e | 2020-08-06 20:06:04 -0700 | [diff] [blame] | 79 | uint16_t stack_pople(cpu_t *cpu) |
| 80 | { |
| 81 | uint8_t a = stack_pop(cpu); |
| 82 | uint8_t b = stack_pop(cpu); |
| 83 | return le_to_native(a, b); |
| 84 | } |
| 85 | |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 86 | void free_cpu(cpu_t *cpu) |
| 87 | { |
| 88 | free(cpu->mem); |
| 89 | } |
| 90 | |
swissChili | da4803e | 2020-08-06 20:06:04 -0700 | [diff] [blame] | 91 | // rotate right |
| 92 | uint8_t ror(uint8_t a, uint8_t n) |
| 93 | { |
| 94 | return (a >> n) | (a << (8 - n)); |
| 95 | } |
| 96 | |
| 97 | // rotate left |
| 98 | uint8_t rol(uint8_t a, uint8_t n) |
| 99 | { |
| 100 | return (a << n) | (a >> (8 - n)); |
| 101 | } |
| 102 | |
swissChili | 6264a3b | 2020-07-30 19:02:07 -0700 | [diff] [blame] | 103 | void stat_nz(cpu_t *cpu, int8_t v) |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 104 | { |
swissChili | 6264a3b | 2020-07-30 19:02:07 -0700 | [diff] [blame] | 105 | cpu->status.negative = v < 0; |
| 106 | cpu->status.zero = v == 0; |
| 107 | } |
| 108 | |
| 109 | // Used to check for overflow, is c unique? |
| 110 | bool last_unique(bool a, bool b, bool c) |
| 111 | { |
| 112 | return a == b && a != c; |
| 113 | } |
| 114 | |
| 115 | void stat_cv(cpu_t *cpu, uint8_t a, uint8_t b, uint8_t c) |
| 116 | { |
| 117 | cpu->status.overflow = last_unique(a >> 7, b >> 7, c >> 7); |
| 118 | cpu->status.carry = c < a || c < b; |
| 119 | } |
| 120 | |
swissChili | da4803e | 2020-08-06 20:06:04 -0700 | [diff] [blame] | 121 | void cmp(cpu_t *cpu, uint8_t reg, uint8_t mem) |
| 122 | { |
| 123 | cpu->status.negative = 0; |
| 124 | cpu->status.zero = 0; |
| 125 | cpu->status.carry = 0; |
| 126 | if (cpu->regs[reg] < mem) |
| 127 | { |
| 128 | cpu->status.negative = 1; |
| 129 | } |
| 130 | else if (cpu->regs[reg] == mem) |
| 131 | { |
| 132 | cpu->status.zero = 1; |
| 133 | cpu->status.carry = 1; |
| 134 | } |
| 135 | else |
| 136 | { |
| 137 | cpu->status.carry = 1; |
| 138 | } |
| 139 | } |
| 140 | |
| 141 | void execute(cpu_t *cpu, const char *mnemonic, uint8_t op, arg_t a, uint8_t am) |
swissChili | 6264a3b | 2020-07-30 19:02:07 -0700 | [diff] [blame] | 142 | { |
| 143 | // used to save space |
| 144 | #define REGS \ |
| 145 | R(X) R(A) R(Y) |
| 146 | |
swissChili | 710d18d | 2020-07-29 19:43:20 -0700 | [diff] [blame] | 147 | switch (op) { |
swissChili | 6264a3b | 2020-07-30 19:02:07 -0700 | [diff] [blame] | 148 | // Load and store instructions: |
| 149 | #define R(reg) \ |
| 150 | case LD##reg: \ |
| 151 | cpu->regs[reg] = a.val; \ |
| 152 | stat_nz(cpu, a.val); \ |
| 153 | break; |
| 154 | |
| 155 | REGS |
| 156 | |
| 157 | #undef R |
| 158 | |
| 159 | #define R(reg) \ |
| 160 | case ST##reg: \ |
| 161 | cpu->mem[a.ptr] = cpu->regs[reg]; \ |
| 162 | break; \ |
| 163 | |
| 164 | REGS |
| 165 | |
| 166 | #undef R |
| 167 | |
| 168 | // Arithmetic instructions: |
| 169 | // NOTE: binary coded decimals are NOT SUPPORTED because I don't want |
| 170 | // to implement them. |
| 171 | case ADC: |
| 172 | { |
| 173 | uint8_t sum = cpu->regs[A] + a.val + cpu->status.carry; |
| 174 | // signed overflow |
| 175 | stat_cv(cpu, cpu->regs[A], a.val + cpu->status.carry, sum); |
| 176 | stat_nz(cpu, sum); |
| 177 | cpu->regs[A] = sum; |
| 178 | break; |
| 179 | } |
| 180 | |
| 181 | case SBC: |
| 182 | { |
| 183 | uint8_t diff = cpu->regs[A] - a.val - !cpu->status.carry; |
| 184 | stat_cv(cpu, cpu->regs[A], a.val - !cpu->status.carry, diff); |
| 185 | stat_nz(cpu, diff); |
| 186 | cpu->regs[A] = diff; |
| 187 | break; |
| 188 | } |
| 189 | |
| 190 | case INC: |
| 191 | cpu->mem[a.ptr]++; |
| 192 | stat_nz(cpu, cpu->mem[a.ptr]); |
| 193 | break; |
| 194 | |
| 195 | case INX: |
| 196 | cpu->regs[X]++; |
| 197 | stat_nz(cpu, cpu->regs[X]); |
| 198 | break; |
| 199 | |
| 200 | case INY: |
| 201 | cpu->regs[Y]++; |
| 202 | stat_nz(cpu, cpu->regs[Y]); |
| 203 | break; |
| 204 | |
| 205 | case DEC: |
| 206 | cpu->mem[a.ptr]--; |
| 207 | stat_nz(cpu, cpu->mem[a.ptr]); |
| 208 | break; |
swissChili | da4803e | 2020-08-06 20:06:04 -0700 | [diff] [blame] | 209 | |
| 210 | case DEX: |
| 211 | cpu->regs[X]--; |
| 212 | stat_nz(cpu, cpu->regs[X]); |
| 213 | break; |
| 214 | |
| 215 | case DEY: |
| 216 | cpu->regs[Y]--; |
| 217 | stat_nz(cpu, cpu->regs[Y]); |
| 218 | break; |
| 219 | |
| 220 | case ASL: |
| 221 | // This check must be done here unfortunately, it would be nice |
| 222 | // to do this while decoding operands but it would require |
| 223 | // a substantial change to the architecture of the emulator |
| 224 | if (am == AM_ACC) |
| 225 | { |
| 226 | cpu->status.carry = cpu->regs[A] >> 7; |
| 227 | cpu->regs[A] <<= 1; |
| 228 | stat_nz(cpu, cpu->regs[A]); |
| 229 | } |
| 230 | else |
| 231 | { |
| 232 | cpu->status.carry = cpu->mem[a.val] >> 7; |
| 233 | cpu->mem[a.ptr] <<= 1; |
| 234 | stat_nz(cpu, cpu->mem[a.ptr]); |
| 235 | } |
| 236 | break; |
| 237 | |
| 238 | case LSR: |
| 239 | if (am == AM_ACC) |
| 240 | { |
| 241 | cpu->status.carry = cpu->regs[A] & 1; |
| 242 | cpu->regs[A] >>= 1; |
| 243 | stat_nz(cpu, cpu->regs[A]); |
| 244 | } |
| 245 | else |
| 246 | { |
| 247 | cpu->status.carry = cpu->mem[a.val] & 7; |
| 248 | cpu->mem[a.ptr] >>= 1; |
| 249 | stat_nz(cpu, cpu->mem[a.ptr]); |
| 250 | } |
| 251 | break; |
| 252 | |
| 253 | case ROL: |
| 254 | if (am == AM_ACC) |
| 255 | { |
| 256 | cpu->status.carry = cpu->regs[A] >> 7; |
| 257 | cpu->regs[A] = rol(cpu->regs[A], 1); |
| 258 | stat_nz(cpu, cpu->regs[A]); |
| 259 | } |
| 260 | else |
| 261 | { |
| 262 | cpu->status.carry = cpu->mem[a.val] >> 7; |
| 263 | cpu->mem[a.ptr] = rol(a.val, 1); |
| 264 | stat_nz(cpu, cpu->mem[a.ptr]); |
| 265 | } |
| 266 | break; |
| 267 | |
| 268 | case ROR: |
| 269 | if (am == AM_ACC) |
| 270 | { |
| 271 | cpu->status.carry = cpu->regs[A] & 1; |
| 272 | cpu->regs[A] = ror(cpu->regs[A], 1); |
| 273 | stat_nz(cpu, cpu->regs[A]); |
| 274 | } |
| 275 | else |
| 276 | { |
| 277 | cpu->status.carry = cpu->mem[a.val] & 1; |
| 278 | cpu->mem[a.ptr] = ror(a.val, 1); |
| 279 | stat_nz(cpu, cpu->mem[a.ptr]); |
| 280 | } |
| 281 | break; |
| 282 | |
| 283 | case AND: |
| 284 | cpu->regs[A] &= a.val; |
| 285 | stat_nz(cpu, cpu->regs[A]); |
| 286 | break; |
| 287 | |
| 288 | case ORA: |
| 289 | cpu->regs[A] |= a.val; |
| 290 | stat_nz(cpu, cpu->regs[A]); |
| 291 | break; |
| 292 | |
| 293 | case EOR: |
| 294 | cpu->regs[A] ^= a.val; |
| 295 | stat_nz(cpu, cpu->regs[A]); |
| 296 | break; |
| 297 | |
| 298 | case CMP: |
| 299 | cmp(cpu, A, a.val); |
| 300 | break; |
| 301 | |
| 302 | case CPX: |
| 303 | cmp(cpu, X, a.val); |
| 304 | break; |
| 305 | |
| 306 | case CPY: |
| 307 | cmp(cpu, Y, a.val); |
| 308 | break; |
| 309 | |
| 310 | // TODO: implement BIT here |
| 311 | |
| 312 | #define BRANCHES \ |
| 313 | B(BCC, carry == 0) \ |
| 314 | B(BCS, carry == 1) \ |
| 315 | B(BNE, zero == 0) \ |
| 316 | B(BEQ, zero == 1) \ |
| 317 | B(BPL, negative == 0) \ |
| 318 | B(BMI, negative == 1) \ |
| 319 | B(BVC, overflow == 0) \ |
| 320 | B(BVS, overflow == 1) |
| 321 | |
| 322 | #define B(i, c) \ |
| 323 | case i: \ |
| 324 | if (cpu->status . c) \ |
| 325 | cpu->pc = a.ptr;\ |
| 326 | break; |
| 327 | |
| 328 | BRANCHES |
| 329 | |
| 330 | #undef B |
| 331 | #undef BRANCHES |
| 332 | |
| 333 | #define TRANSFERS \ |
| 334 | T(A, X) \ |
| 335 | T(X, A) \ |
| 336 | T(A, Y) \ |
| 337 | T(Y, A) |
| 338 | |
| 339 | #define T(a, b) \ |
| 340 | case T ## a ## b: \ |
| 341 | cpu->regs[b] = cpu->regs[a]; \ |
| 342 | stat_nz(cpu, cpu->regs[b]); \ |
| 343 | break; |
| 344 | |
| 345 | TRANSFERS |
| 346 | |
| 347 | #undef T |
| 348 | #undef TRANSFERS |
| 349 | |
| 350 | case TSX: |
| 351 | cpu->regs[X] = cpu->regs[SP]; |
| 352 | stat_nz(cpu, cpu->regs[X]); |
| 353 | break; |
| 354 | |
| 355 | case TXS: |
| 356 | cpu->regs[SP] = cpu->regs[X]; |
| 357 | stat_nz(cpu, cpu->regs[X]); |
| 358 | break; |
| 359 | |
| 360 | case PHA: |
| 361 | stack_push(cpu, cpu->regs[A]); |
| 362 | break; |
| 363 | |
| 364 | case PLA: |
| 365 | cpu->regs[A] = stack_pop(cpu); |
| 366 | stat_nz(cpu, cpu->regs[A]); |
| 367 | break; |
| 368 | |
| 369 | case PHP: |
| 370 | stack_push(cpu, *(uint8_t *)(&cpu->status)); |
| 371 | break; |
| 372 | |
| 373 | case PLP: |
| 374 | { |
| 375 | uint8_t s = stack_pop(cpu); |
| 376 | *(uint8_t *)(&cpu->status) = s; |
| 377 | } |
| 378 | |
| 379 | case JMP: |
| 380 | cpu->pc = a.ptr; |
| 381 | break; |
| 382 | |
| 383 | case JSR: |
| 384 | stack_pushle(cpu, cpu->pc); |
| 385 | break; |
| 386 | |
| 387 | case RTS: |
| 388 | cpu->pc = stack_pople(cpu); |
| 389 | break; |
| 390 | |
| 391 | // TODO: implement RTI |
| 392 | // TODO: implement flag instructions |
| 393 | |
| 394 | case BRK: |
| 395 | // TODO: trigger an interrupt |
| 396 | cpu->running = false; |
| 397 | break; |
| 398 | |
| 399 | case NOP: |
| 400 | break; |
| 401 | |
| 402 | default: |
| 403 | die("Unsupported opcode: %x\n", op); |
swissChili | 710d18d | 2020-07-29 19:43:20 -0700 | [diff] [blame] | 404 | } |
swissChili | 6264a3b | 2020-07-30 19:02:07 -0700 | [diff] [blame] | 405 | #undef REGS |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 406 | } |
| 407 | |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 408 | uint16_t fetch_le(cpu_t *cpu) |
| 409 | { |
| 410 | uint8_t a = cpu->mem[cpu->pc++]; |
| 411 | uint8_t b = cpu->mem[cpu->pc++]; |
| 412 | return le_to_native(a, b); |
| 413 | } |
| 414 | |
swissChili | 710d18d | 2020-07-29 19:43:20 -0700 | [diff] [blame] | 415 | arg_t arg_imm(uint16_t a) |
| 416 | { |
| 417 | return (arg_t){ a, a }; |
| 418 | } |
| 419 | |
| 420 | arg_t arg_ptr(cpu_t *c, uint flags, uint16_t p) |
| 421 | { |
| 422 | if (flags & FETCH_NO_INDIRECTION) |
| 423 | return arg_imm(p); |
| 424 | |
| 425 | return (arg_t){ c->mem[p], p }; |
| 426 | } |
| 427 | |
| 428 | arg_t arg(uint16_t v, uint16_t a) |
| 429 | { |
| 430 | return (arg_t){ v, a }; |
| 431 | } |
| 432 | |
| 433 | arg_t fetch_addr(cpu_t *cpu, uint8_t am, uint f) |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 434 | { |
| 435 | switch (am) |
| 436 | { |
| 437 | case AM_ACC: |
| 438 | case AM_IMP: |
swissChili | 710d18d | 2020-07-29 19:43:20 -0700 | [diff] [blame] | 439 | return arg_imm(0); |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 440 | |
| 441 | // In both cases return immediate 8 bit value |
| 442 | case AM_IMM: |
| 443 | case AM_ZP: |
swissChili | 710d18d | 2020-07-29 19:43:20 -0700 | [diff] [blame] | 444 | return arg_imm(cpu->mem[cpu->pc++]); |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 445 | |
| 446 | case AM_ABS: |
swissChili | 710d18d | 2020-07-29 19:43:20 -0700 | [diff] [blame] | 447 | return arg_ptr(cpu, f, fetch_le(cpu)); |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 448 | |
| 449 | case AM_REL: |
| 450 | { |
swissChili | 6264a3b | 2020-07-30 19:02:07 -0700 | [diff] [blame] | 451 | // Aparently, PC should will point to the NEXT opcode |
| 452 | // I can't find any documentation on this unfortunately, but |
| 453 | // I have discovered this through testing the output of other |
| 454 | // assemblers. |
| 455 | uint16_t pc = cpu->pc + 1; |
| 456 | return arg_ptr(cpu, f, (int8_t)cpu->mem[cpu->pc++] + pc); |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 457 | } |
| 458 | |
| 459 | case AM_IND: |
| 460 | { |
| 461 | uint16_t addr = fetch_le(cpu); |
swissChili | 6264a3b | 2020-07-30 19:02:07 -0700 | [diff] [blame] | 462 | |
| 463 | if (f & FETCH_NO_INDIRECTION) |
| 464 | return arg_imm(addr); |
| 465 | |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 466 | uint8_t low = cpu->mem[addr], |
| 467 | high = cpu->mem[addr + 1]; |
| 468 | |
swissChili | 710d18d | 2020-07-29 19:43:20 -0700 | [diff] [blame] | 469 | return arg_ptr(cpu, f, le_to_native(low, high)); |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 470 | } |
| 471 | |
| 472 | case AM_AX: |
swissChili | 710d18d | 2020-07-29 19:43:20 -0700 | [diff] [blame] | 473 | return arg_ptr(cpu, f, fetch_le(cpu) + cpu->regs[X]); |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 474 | |
| 475 | case AM_AY: |
swissChili | 710d18d | 2020-07-29 19:43:20 -0700 | [diff] [blame] | 476 | return arg_ptr(cpu, f, fetch_le(cpu) + cpu->regs[Y]); |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 477 | |
| 478 | case AM_ZPX: |
swissChili | 710d18d | 2020-07-29 19:43:20 -0700 | [diff] [blame] | 479 | return arg_ptr(cpu, f, cpu->mem[cpu->pc++] + cpu->regs[X]); |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 480 | |
| 481 | case AM_ZPY: |
swissChili | 710d18d | 2020-07-29 19:43:20 -0700 | [diff] [blame] | 482 | return arg_ptr(cpu, f, cpu->mem[cpu->pc++] + cpu->regs[Y]); |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 483 | |
| 484 | case AM_ZIX: |
| 485 | { |
| 486 | uint8_t zp = cpu->mem[cpu->pc++]; |
swissChili | 6264a3b | 2020-07-30 19:02:07 -0700 | [diff] [blame] | 487 | |
| 488 | if (f & FETCH_NO_INDIRECTION) |
| 489 | return arg_imm(zp); |
| 490 | |
swissChili | 710d18d | 2020-07-29 19:43:20 -0700 | [diff] [blame] | 491 | uint16_t addr = zp + cpu->regs[X]; |
| 492 | uint16_t indirect = le_to_native(cpu->mem[addr], cpu->mem[addr + 1]); |
| 493 | return arg_ptr(cpu, f, indirect); |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 494 | } |
| 495 | |
| 496 | case AM_ZIY: |
| 497 | { |
| 498 | uint8_t zp = cpu->mem[cpu->pc++]; |
swissChili | 6264a3b | 2020-07-30 19:02:07 -0700 | [diff] [blame] | 499 | |
| 500 | if (f & FETCH_NO_INDIRECTION) |
| 501 | return arg_imm(zp); |
| 502 | |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 503 | uint16_t base = le_to_native(cpu->mem[zp], cpu->mem[zp + 1]); |
swissChili | 710d18d | 2020-07-29 19:43:20 -0700 | [diff] [blame] | 504 | return arg_ptr(cpu, f, base + cpu->regs[Y]); |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 505 | } |
| 506 | |
| 507 | default: |
| 508 | die("Unknown address mode %x", am); |
swissChili | 710d18d | 2020-07-29 19:43:20 -0700 | [diff] [blame] | 509 | __builtin_unreachable(); |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 510 | } |
| 511 | } |
| 512 | |
| 513 | void step(cpu_t *cpu) |
| 514 | { |
| 515 | switch (cpu->mem[cpu->pc++]) |
| 516 | { |
| 517 | #define INST(mn, am, op) \ |
| 518 | case op: \ |
swissChili | da4803e | 2020-08-06 20:06:04 -0700 | [diff] [blame] | 519 | execute(cpu, #mn, mn, fetch_addr(cpu, am, 0), am); \ |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 520 | break; |
| 521 | |
| 522 | INSTRUCTIONS |
| 523 | |
| 524 | #undef INST |
| 525 | |
| 526 | default: |
| 527 | die("Undefined opcode"); |
| 528 | } |
| 529 | } |
| 530 | |
| 531 | void dump_inst(cpu_t *cpu, const char *mn, uint16_t addr, uint8_t am) |
| 532 | { |
| 533 | printf("\t%s\t", mn); |
| 534 | |
| 535 | switch (am) |
| 536 | { |
| 537 | case AM_IMM: |
| 538 | printf("#"); |
| 539 | case AM_REL: |
| 540 | case AM_ABS: |
| 541 | case AM_ZP: |
| 542 | printf("$%x", addr); |
| 543 | break; |
| 544 | |
| 545 | case AM_IND: |
| 546 | printf("($%x)", addr); |
| 547 | break; |
| 548 | |
| 549 | case AM_AX: |
| 550 | case AM_ZPX: |
| 551 | printf("$%x, X", addr); |
| 552 | break; |
| 553 | |
| 554 | case AM_AY: |
| 555 | case AM_ZPY: |
| 556 | printf("$%x, Y", addr); |
| 557 | break; |
| 558 | |
| 559 | case AM_ZIX: |
| 560 | printf("($%x, X)", addr); |
| 561 | break; |
| 562 | |
| 563 | case AM_ZIY: |
| 564 | printf("($%x), Y", addr); |
| 565 | break; |
| 566 | } |
| 567 | |
| 568 | printf("\n"); |
| 569 | } |
| 570 | |
| 571 | void disas_step(cpu_t *cpu) |
| 572 | { |
swissChili | 6264a3b | 2020-07-30 19:02:07 -0700 | [diff] [blame] | 573 | printf("$%x", cpu->pc); |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 574 | uint8_t op = cpu->mem[cpu->pc++]; |
| 575 | switch (op) |
| 576 | { |
| 577 | #define INST(mn, am, op) \ |
| 578 | case op: \ |
swissChili | 710d18d | 2020-07-29 19:43:20 -0700 | [diff] [blame] | 579 | dump_inst(cpu, #mn, \ |
| 580 | fetch_addr(cpu, am, FETCH_NO_INDIRECTION).ptr, am); \ |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 581 | break; |
| 582 | |
| 583 | INSTRUCTIONS |
| 584 | |
| 585 | #undef INST |
| 586 | |
| 587 | default: |
swissChili | 6264a3b | 2020-07-30 19:02:07 -0700 | [diff] [blame] | 588 | warn("\tUndefined opcode %x", op); |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 589 | } |
| 590 | } |
| 591 | |
swissChili | da4803e | 2020-08-06 20:06:04 -0700 | [diff] [blame] | 592 | void disas_num(cpu_t *cpu, uint16_t num) |
| 593 | { |
| 594 | for (int i = 0; i < num; i++) |
| 595 | { |
| 596 | disas_step(cpu); |
| 597 | } |
| 598 | } |
| 599 | |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 600 | void disas(cpu_t *cpu) |
| 601 | { |
swissChili | 6264a3b | 2020-07-30 19:02:07 -0700 | [diff] [blame] | 602 | // Raw binary, no way to know what's code what isn't |
swissChili | 6c61a79 | 2020-07-28 16:29:20 -0700 | [diff] [blame] | 603 | while (cpu->pc < 0xFFFF) |
| 604 | { |
| 605 | disas_step(cpu); |
| 606 | } |
| 607 | } |
swissChili | da4803e | 2020-08-06 20:06:04 -0700 | [diff] [blame] | 608 | void run(cpu_t *cpu) |
| 609 | { |
| 610 | while (cpu->running) |
| 611 | { |
| 612 | step(cpu); |
| 613 | } |
| 614 | |
| 615 | printf("CPU Halted\n"); |
| 616 | } |