diff --git a/README.md b/README.md
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+# Searchable RISC-V instruction reference
+
+Generated from the great documentation written by
+[~icefox](https://hg.sr.ht/~icefox/riscv-reference) on sourcehut.
+
+See it online [here](https://repo.swisschili.sh/riscv-reference).
diff --git a/index.html b/index.html
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+<!DOCTYPE html>
+
+<div class="wrapper">
+<input type="text" id="searchbox" placeholder="Search RISC-V Instructions"></input>
+</div>
+
+<div id="ilist">
+</div>
+
+<hr>
+
+<p class="cite">
+	These listings are generated from documentation written
+	by <a href="https://hg.sr.ht/~icefox/riscv-reference">~icefox</a>
+	on sourcehut. Website created by <a href="https://swisschili.sh">swissChili</a>.
+</p>
+<p class="cite">
+	This documentation is incomplete for now. Check the ~icefox link
+	for what is currently implemented.
+</p>
+
+<style>
+ body {
+	 font-family: sans-serif;
+	 max-width: 50em;
+	 margin: auto;
+	 padding: 10px;
+ }
+
+ dt {
+	 font-weight: bold;
+ }
+
+ dd div,
+ #searchbox {
+	 background: #fcfaf2;
+	 padding: 4px;
+	 border-radius: 4px;
+	 border: 1px solid #f4f2e8;
+ }
+
+ #searchbox {
+	 font-size: 14pt;
+	 padding: 12px 20px;
+	 width: min-content;
+ }
+
+ .wrapper {
+	 width: 100%;
+	 display: flex;
+	 justify-content: center;
+	 margin-bottom: 4em;
+	 margin-top: 2em;
+ }
+
+ .cite {
+	 font-style: italic;
+	 text-align: center;
+ }
+
+ hr {
+	 border-color: #CCC;
+ }
+</style>
+
+<script>
+ function setup(instructions)
+ {
+	 console.log(instructions);
+
+	 function handler()
+	 {
+		 let html = "";
+
+		 console.log("searched");
+
+		 let q = searchbox.value.toLowerCase();
+
+		 console.log({q});
+
+		 for (let item of instructions)
+		 {
+			 if (!item.mnemonic.toLowerCase().includes(q) &&
+				 !item.name.toLowerCase().includes(q))
+				 continue;
+
+			 let desc = item.long_description.replace("\n\n", "</p><p>");
+
+			 html += `
+			 <dt>${item.mnemonic} - ${item.name}</dt>
+			 <dd>
+				 <div>encoding: ${item.encoding}, extension: ${item.extension}, opcode: ${item.opcode}</div>
+				 <p>${desc}</p>
+			 </dd>
+			 `;
+		 }
+
+		 ilist.innerHTML = html;
+	 };
+
+	 searchbox.addEventListener("input", handler);
+	 handler();
+ }
+ 
+ fetch("instructions.json")
+	 .then(res => res.json())
+	 .then(setup);
+</script>
diff --git a/instructions.json b/instructions.json
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+[{"name": "Add immediate", "opcode": "OP-IMM / ADDI", "encoding": "I", "extension": "I", "long_description": "ADDI adds the sign-extended 12-bit immediate to register rs1. Arithmetic overflow is ignored and\nthe result is simply the low XLEN bits of the result. ADDI rd, rs1, 0 is used to implement the MV\nrd, rs1 assembler pseudoinstruction.\n", "mnemonic": "ADDI"}, {"name": "Set less than immediate", "opcode": "OP-IMM / SLTI", "encoding": "I", "extension": "I", "long_description": "SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the signextended immediate when both are treated as signed numbers, else 0 is written to rd. SLTIU is\nsimilar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to\nXLEN bits then treated as an unsigned number). Note, SLTIU rd, rs1, 1 sets rd to 1 if rs1 equals\nzero, otherwise sets rd to 0 (assembler pseudoinstruction SEQZ rd, rs)\n", "mnemonic": "SLTI"}, {"name": "Set less than immediate unsigned", "opcode": "OP-IMM / SLTIU", "encoding": "I", "extension": "I", "long_description": "SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the signextended immediate when both are treated as signed numbers, else 0 is written to rd. SLTIU is\nsimilar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to\nXLEN bits then treated as an unsigned number). Note, SLTIU rd, rs1, 1 sets rd to 1 if rs1 equals\nzero, otherwise sets rd to 0 (assembler pseudoinstruction SEQZ rd, rs)\n", "mnemonic": "SLTIU"}, {"name": "AND immediate", "opcode": "OP-IMM / ANDI", "encoding": "I", "extension": "I", "long_description": "ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1\nand the sign-extended 12-bit immediate and place the result in rd. Note, XORI rd, rs1, -1 performs\na bitwise logical inversion of register rs1 (assembler pseudoinstruction\nNOT rd, rs).\n", "mnemonic": "ANDI"}, {"name": "OR immediate", "opcode": "OP-IMM / ORI", "encoding": "I", "extension": "I", "long_description": "ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1\nand the sign-extended 12-bit immediate and place the result in rd. Note, XORI rd, rs1, -1 performs\na bitwise logical inversion of register rs1 (assembler pseudoinstruction\nNOT rd, rs).\n", "mnemonic": "ORI"}, {"name": "XOR immediate", "opcode": "OP-IMM / XORI", "encoding": "I", "extension": "I", "long_description": "ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1\nand the sign-extended 12-bit immediate and place the result in rd. Note, XORI rd, rs1, -1 performs\na bitwise logical inversion of register rs1 (assembler pseudoinstruction\nNOT rd, rs).\n", "mnemonic": "XORI"}, {"name": "Shift left logical immediate", "opcode": "OP-IMM / SLLI", "encoding": "I", "extension": "I", "long_description": "Shifts by a constant are encoded as a specialization of the I-type\nformat.  The operand to be shiftedis inrs1, and the shift amount is\nencoded in the lower 5 bits of the I-immediate field.  The rightshift\ntype is encoded in bit 30.  SLLI is a logical left shift (zeros are\nshifted into the lower bits); SRLI is a logical right shift (zeros are\nshifted into the upper bits); and SRAI is an arithmetic rightshift (the\noriginal sign bit is copied into the vacated upper bits).\n", "mnemonic": "SLLI"}, {"name": "Shift right logical immediate", "opcode": "OP-IMM / SRLI", "encoding": "I", "extension": "I", "long_description": "Shifts by a constant are encoded as a specialization of the I-type\nformat.  The operand to be shiftedis inrs1, and the shift amount is\nencoded in the lower 5 bits of the I-immediate field.  The rightshift\ntype is encoded in bit 30.  SLLI is a logical left shift (zeros are\nshifted into the lower bits); SRLI is a logical right shift (zeros are\nshifted into the upper bits); and SRAI is an arithmetic rightshift (the\noriginal sign bit is copied into the vacated upper bits).\n", "mnemonic": "SRLI"}, {"name": "Shift right arithmetic immediate", "opcode": "OP-IMM / SRAI", "encoding": "I", "extension": "I", "long_description": "Shifts by a constant are encoded as a specialization of the I-type\nformat.  The operand to be shiftedis inrs1, and the shift amount is\nencoded in the lower 5 bits of the I-immediate field.  The rightshift\ntype is encoded in bit 30.  SLLI is a logical left shift (zeros are\nshifted into the lower bits); SRLI is a logical right shift (zeros are\nshifted into the upper bits); and SRAI is an arithmetic rightshift (the\noriginal sign bit is copied into the vacated upper bits).\n", "mnemonic": "SRAI"}, {"name": "Load upper immediate", "opcode": "LUI", "encoding": "U", "extension": "I", "long_description": "LUI (load upper immediate) is used to build 32-bit constants and uses the U-type format.  LUIplaces the U-immediate value in the top 20 bits of the destination registerrd, filling in the lowest12 bits with zeros.\n", "mnemonic": "LUI"}, {"name": "Add upper immediate to PC", "opcode": "AUIPC", "encoding": "U", "extension": "I", "long_description": "AUIPC (add upper immediate topc) is used to buildpc-relative addresses and uses the U-typeformat.  AUIPC forms a 32-bit offset from the 20-bit U-immediate, filling in the lowest 12 bits withzeros, adds this offset to the address of the AUIPC instruction, then places the result in registerrd.\n", "mnemonic": "AUIPC"}, {"name": "Add", "opcode": "OP / ADD / 0", "encoding": "R", "extension": "I", "long_description": "ADD performs the addition of rs 1andrs2. SUB performs the subtraction of rs2 from rs1. Overflow sare ignored and the low XLEN bits of results are written to the destination rd.\n", "mnemonic": "ADD"}, {"name": "SUB", "opcode": "OP / SUB / 0b0100000", "encoding": "R", "extension": "I", "long_description": "ADD performs the addition of rs 1andrs2. SUB performs the subtraction of rs2 from rs1. Overflow sare ignored and the low XLEN bits of results are written to the destination rd.\n", "mnemonic": "SUB"}, {"name": "Signed less than compare", "opcode": "OP / SLT / 0", "encoding": "R", "extension": "I", "long_description": "SLT and SLTU perform signed and unsigned compares respectively, writing 1 tordifrs1<rs2, 0 otherwise.  Note,\nSLTU rd,x0,rs2 sets rd to  1  if rs2 is  not  equal  to  zero,  otherwise  sets rd to  zero  (assembler pseudoinstruction SNEZ rd, rs).\n", "mnemonic": "SLT"}, {"name": "Signed less than compare unsigned", "opcode": "OP / SLTU / 0", "encoding": "R", "extension": "I", "long_description": "SLT and SLTU perform signed and unsigned compares respectively, writing 1 tordifrs1<rs2, 0 otherwise.  Note,\nSLTU rd,x0,rs2 sets rd to  1  if rs2 is  not  equal  to  zero,  otherwise  sets rd to  zero  (assembler pseudoinstruction SNEZ rd, rs).\n", "mnemonic": "SLTU"}, {"name": "AND", "opcode": "OP / AND / 0", "encoding": "R", "extension": "I", "long_description": "AND, OR, and XOR perform bitwise logical operations.\n", "mnemonic": "AND"}, {"name": "OR", "opcode": "OP / OR / 0", "encoding": "R", "extension": "I", "long_description": "AND, OR, and XOR perform bitwise logical operations.\n", "mnemonic": "OR"}, {"name": "XOR", "opcode": "OP / XOR / 0", "encoding": "R", "extension": "I", "long_description": "AND, OR, and XOR perform bitwise logical operations.\n", "mnemonic": "XOR"}, {"name": "Shift left logical", "opcode": "OP / SLL / 0", "encoding": "R", "extension": "I", "long_description": "SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value inregister rs1 by the shift amount held in the lower 5 bits of register rs2\n", "mnemonic": "SLL"}, {"name": "Shift right logical", "opcode": "OP / SRL / 0", "encoding": "R", "extension": "I", "long_description": "SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value inregister rs1 by the shift amount held in the lower 5 bits of register rs2\n", "mnemonic": "SRL"}, {"name": "Shift right arithmetic", "opcode": "OP / SRA / 0b0100000", "encoding": "R", "extension": "I", "long_description": "SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value inregister rs1 by the shift amount held in the lower 5 bits of register rs2\n", "mnemonic": "SRA"}, {"name": "No operation", "opcode": "OP-IMM / ADDI", "encoding": "I", "extension": "I", "long_description": "The NOP instruction does not change any architecturally visible state, except for advancing the pc and incrementing any applicable performance counters.  NOP is encoded as ADDI x0, x0, 0.\n", "mnemonic": "NOP"}, {"name": "Unconditional jump", "opcode": "JAL", "encoding": "J", "extension": "I", "long_description": "Plain unconditional jumps (assembler pseudoinstruction J) are encoded as\na JAL with rd=x0.\n", "mnemonic": "J"}, {"name": "Jump and link", "opcode": "JAL", "encoding": "J", "extension": "I", "long_description": "The  jump  and  link  (JAL)  instruction  uses  the  J-type  format,  where  the  J-immediate  encodes  asigned offset in multiples of 2 bytes.  The offset is sign-extended and added to the address of thejump instruction to form the jump target address.  Jumps can therefore target a\u00b11 MiB range.  JAL stores the address of the instruction following the jump (pc+4) into register rd.  The standard software calling convention uses x1 as the return address register and x5 as an alternate link register\n", "mnemonic": "JAL"}, {"name": "Jump and link register", "opcode": "JAL", "encoding": "I", "extension": "I", "long_description": "The indirect jump instruction JALR (jump and link register) uses the I-type encoding. The target\naddress is obtained by adding the sign-extended 12-bit I-immediate to the register rs1, then setting\nthe least-significant bit of the result to zero. The address of the instruction following the jump\n(pc+4) is written to register rd. Register x0 can be used as the destination if the result is not\nrequired.\n", "mnemonic": "JALR"}, {"name": "Branch if equal", "opcode": "BRANCH / BEQ", "encoding": "B", "extension": "I", "long_description": "Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2\nare equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using\nsigned and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater\nthan or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU,\nBLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU,\nrespectively\n", "mnemonic": "BEQ"}, {"name": "Branch if not equal", "opcode": "BRANCH / BNE", "encoding": "B", "extension": "I", "long_description": "Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2\nare equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using\nsigned and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater\nthan or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU,\nBLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU,\nrespectively\n", "mnemonic": "BNE"}, {"name": "Branch if less than", "opcode": "BRANCH / BLT", "encoding": "B", "extension": "I", "long_description": "Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2\nare equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using\nsigned and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater\nthan or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU,\nBLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU,\nrespectively\n", "mnemonic": "BLT"}, {"name": "Branch if less than unsigned", "opcode": "BRANCH / BLTU", "encoding": "B", "extension": "I", "long_description": "Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2\nare equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using\nsigned and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater\nthan or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU,\nBLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU,\nrespectively\n", "mnemonic": "BLTU"}, {"name": "Branch if greater or equal", "opcode": "BRANCH / BGE", "encoding": "B", "extension": "I", "long_description": "Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2\nare equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using\nsigned and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater\nthan or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU,\nBLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU,\nrespectively\n", "mnemonic": "BGE"}, {"name": "Branch if greater or equal unsigned", "opcode": "BRANCH / BGEU", "encoding": "B", "extension": "I", "long_description": "Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2\nare equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using\nsigned and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater\nthan or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU,\nBLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU,\nrespectively\n", "mnemonic": "BGEU"}, {"name": "Load word", "opcode": "LOAD / width", "encoding": "I", "extension": "I", "long_description": "The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory,\nthen sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then\nzero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values.\n", "mnemonic": "LW"}, {"name": "Load half word", "opcode": "LOAD / width", "encoding": "I", "extension": "I", "long_description": "The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory,\nthen sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then\nzero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values.\n", "mnemonic": "LH"}, {"name": "Load half word unsigned", "opcode": "LOAD / width", "encoding": "I", "extension": "I", "long_description": "The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory,\nthen sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then\nzero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values.\n", "mnemonic": "LHU"}, {"name": "Load byte", "opcode": "LOAD / width", "encoding": "I", "extension": "I", "long_description": "The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory,\nthen sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then\nzero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values.\n", "mnemonic": "LB"}, {"name": "Load byte unsigned", "opcode": "LOAD / width", "encoding": "I", "extension": "I", "long_description": "The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory,\nthen sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then\nzero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values.\n", "mnemonic": "LBU"}, {"name": "Store word", "opcode": "STORE / width", "encoding": "S", "extension": "I", "long_description": "The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register\nrs2 to memory\n", "mnemonic": "SW"}, {"name": "Store half word", "opcode": "STORE / width", "encoding": "S", "extension": "I", "long_description": "The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register\nrs2 to memory\n", "mnemonic": "SH"}, {"name": "Store byte", "opcode": "STORE / width", "encoding": "S", "extension": "I", "long_description": "The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register\nrs2 to memory\n", "mnemonic": "SB"}, {"name": "Fence", "opcode": "MISC-MEM / FENCE", "encoding": "I", "extension": "I", "long_description": "The FENCE instruction is used to order device I/O and memory accesses as\nviewed by other RISCV harts and external devices or coprocessors. Any\ncombination of device input (I), device output (O), memory reads (R),\nand memory writes (W) may be ordered with respect to any combination of\nthe same. Informally, no other RISC-V hart or external device can\nobserve any operation in the successor set following a FENCE before any\noperation in the predecessor set preceding the FENCE. Chapter 14\nprovides a precise description of the RISC-V memory consistency model\n", "mnemonic": "FENCE"}, {"name": "Environment call", "opcode": "SYSTEM / PRIV / ECALL", "encoding": "I", "extension": "I", "long_description": "The ECALL instruction is used to make a service request to the execution environment. The EEI\nwill define how parameters for the service request are passed, but usually these will be in defined\nlocations in the integer register file\n", "mnemonic": "ECALL"}, {"name": "Environment break point", "opcode": "SYSTEM / PRIV / EBREAK", "encoding": "I", "extension": "I", "long_description": "The EBREAK instruction is used to return control to a debugging environment.\n", "mnemonic": "EBREAK"}, {"name": "Hint", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "RV32I reserves a large encoding space for HINT instructions, which are usually used to communicate performance hints to the microarchitecture. HINTs are encoded as integer computational\ninstructions with rd=x0. Hence, like the NOP instruction, HINTs do not change any architecturally\nvisible state, except for advancing the pc and any applicable performance counters. Implementations are always allowed to ignore the encoded hints.\n", "mnemonic": "HINT"}, {"name": "Fence", "opcode": "MISC-MEM / FENCE.I", "encoding": "I", "extension": "Zifencei", "long_description": "The FENCE.I instruction is used to synchronize the instruction and data streams. RISC-V does\nnot guarantee that stores to instruction memory will be made visible to instruction fetches on a\nRISC-V hart until that hart executes a FENCE.I instruction. A FENCE.I instruction ensures that\na subsequent instruction fetch on a RISC-V hart will see any previous data stores already visible to\nthe same RISC-V hart. FENCE.I does not ensure that other RISC-V harts\u2019 instruction fetches will\nobserve the local hart\u2019s stores in a multiprocessor system. To make a store to instruction memory\nvisible to all RISC-V harts, the writing hart has to execute a data FENCE before requesting that\nall remote RISC-V harts execute a FENCE.I.\n\nThe unused fields in the FENCE.I instruction, imm[11:0], rs1, and rd, are reserved for finer-grain\nfences in future extensions. For forward compatibility, base implementations shall ignore these\nfields, and standard software shall zero these fields.\n", "mnemonic": "FENCE.I"}, {"name": "Add immediate word", "opcode": "OP-IMM-32 / ADDIW", "encoding": "I", "extension": "I", "long_description": "ADDIW is an RV64I instruction that adds the sign-extended 12-bit immediate to register rs1\nand produces the proper sign-extension of a 32-bit result in rd. Overflows are ignored and the\nresult is the low 32 bits of the result sign-extended to 64 bits. Note, ADDIW rd, rs1, 0 writes\nthe sign-extension of the lower 32 bits of register rs1 into register rd (assembler pseudoinstruction\nSEXT.W)\n", "mnemonic": "ADDIW"}, {"name": "Shift left logical immediate word", "opcode": "OP-IMM-32 / SLLIW", "encoding": "I", "extension": "I", "long_description": "SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate\non 32-bit values and produce signed 32-bit results. SLLIW, SRLIW, and SRAIW encodings with\nimm[5] \u0338= 0 are reserved.\n", "mnemonic": "SLLIW"}, {"name": "Shift right logical immediate word", "opcode": "OP-IMM-32 / SLLIW", "encoding": "I", "extension": "I", "long_description": "SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate\non 32-bit values and produce signed 32-bit results. SLLIW, SRLIW, and SRAIW encodings with\nimm[5] \u0338= 0 are reserved.\n", "mnemonic": "SRLIW"}, {"name": "Shift right arithmetic immediate word", "opcode": "OP-IMM-32 / SRAIW", "encoding": "I", "extension": "I", "long_description": "SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate\non 32-bit values and produce signed 32-bit results. SLLIW, SRLIW, and SRAIW encodings with\nimm[5] \u0338= 0 are reserved.\n", "mnemonic": "SRAIW"}, {"name": "Add word", "opcode": "OP-32 / ADDW", "encoding": "R", "extension": "I", "long_description": "ADDW and SUBW are RV64I-only instructions that are defined analogously to ADD and SUB\nbut operate on 32-bit values and produce signed 32-bit results. Overflows are ignored, and the low\n32-bits of the result is sign-extended to 64-bits and written to the destination register\n", "mnemonic": "ADDW"}, {"name": "Subtract word", "opcode": "OP-32 / SUBW", "encoding": "R", "extension": "I", "long_description": "ADDW and SUBW are RV64I-only instructions that are defined analogously to ADD and SUB\nbut operate on 32-bit values and produce signed 32-bit results. Overflows are ignored, and the low\n32-bits of the result is sign-extended to 64-bits and written to the destination register\n", "mnemonic": "SUBW"}, {"name": "Shift left logical word", "opcode": "OP-32 / SLLW", "encoding": "R", "extension": "I", "long_description": "SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate\non 32-bit values and produce signed 32-bit results. The shift amount is given by rs2[4:0]\n", "mnemonic": "SLLW"}, {"name": "Shift right logical word", "opcode": "OP-32 / SRLW", "encoding": "R", "extension": "I", "long_description": "SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate\non 32-bit values and produce signed 32-bit results. The shift amount is given by rs2[4:0]\n", "mnemonic": "SRLW"}, {"name": "Shift right arithmetic word", "opcode": "OP-32 / SRAW", "encoding": "R", "extension": "I", "long_description": "SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate\non 32-bit values and produce signed 32-bit results. The shift amount is given by rs2[4:0]\n", "mnemonic": "SRAW"}, {"name": "Load absolute address", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "Load absolute address, where delta = symbol \u2212 pc.\n\nNon-position-independent version:\nauipc rd, delta[31 : 12] + delta[11]\naddi rd, rd, delta[11:0]\n\nPosition-independent version:\nauipc rd, delta[31 : 12] + delta[11]\nl{w|d} rd, rd, delta[11:0]\n\n", "mnemonic": "LA"}, {"name": "Load local address", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "Load local address, where delta = symbol \u2212 pc\n\nauipc rd, delta[31 : 12] + delta[11]\naddi rd, rd, delta[11:0]\n", "mnemonic": "LLA"}, {"name": "Load global byte/halfword/word/double", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "Load global\n\nauipc rd, delta[31 : 12] + delta[11]\nl{b|h|w|d} rd, delta[11:0](rd)\n", "mnemonic": "LB/LH/LW/LD"}, {"name": "Store global byte/halfword/word/double", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "Store global\n\nauipc rt, delta[31 : 12] + delta[11]\ns{b|h|w|d} rd, delta[11:0](rt)\n", "mnemonic": "SB/SH/SW/SD"}, {"name": "Load immediate", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "Load immediate.  Expands to \"myriad sequences\".\n", "mnemonic": "LI"}, {"name": "Move", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "Copy register\n\nadd rd, rs, 0\n", "mnemonic": "MV"}, {"name": "One's complement negate", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "One's complement negation.\n\nxori rd, rs, -1\n", "mnemonic": "NOT"}, {"name": "Two's complement negate", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "Two's complement negation.\n\nsub rd, x0, rs\n", "mnemonic": "NEG"}, {"name": "Two's complement negate word", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "Two's complement negation, word length.\n\nsubw rd, x0, rs\n", "mnemonic": "NEGW"}, {"name": "Sign extend word", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "Sign extend word\n\naddiw rd, rs, 0\n", "mnemonic": "SEXT.W"}, {"name": "Set if equal to zero", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "sltiu rd, rs, 1\n", "mnemonic": "SEQZ"}, {"name": "Set if not equal zero", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "sltu rd, x0, rs\n", "mnemonic": "SNEZ"}, {"name": "Set if less than zero", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "slt rd, rs, x0\n", "mnemonic": "SLTZ"}, {"name": "Set if greater than zero", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "lst rd, x0, rs\n", "mnemonic": "SGTZ"}, {"name": "Branch if equal to zero", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "beq rs, x0, offset\n", "mnemonic": "BEQZ"}, {"name": "Branch if not equal zero", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "bne rs, x0, offset\n", "mnemonic": "BNEZ"}, {"name": "Branch if less than zero", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "bge x0, rs, offset\n", "mnemonic": "BLEZ"}, {"name": "Branch if greater or equal to zero", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "bge rs, x0, offset\n", "mnemonic": "BGEZ"}, {"name": "Branch if less than zero", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "blt rs, x0, offset\n", "mnemonic": "BLTZ"}, {"name": "Branch if greater than zero", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "blt x0, rs, offset\n", "mnemonic": "BGTZ"}, {"name": "Branch if greater than", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "blt rt, rs, offset\n", "mnemonic": "BTG"}, {"name": "Branch if less than or equal", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "bge rt, rs, offset\n", "mnemonic": "BLE"}, {"name": "Branch if greater than, unsigned", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "bltu rt, rs, offset\n", "mnemonic": "BGTU"}, {"name": "Branch if less than, unsigned", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "bgeu rt, rs, offset\n", "mnemonic": "BLEU"}, {"name": "Jump register", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "jalr x0, 0(rs)\n", "mnemonic": "JR"}, {"name": "Return from subroutine", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "jalr x0, 0(x1)\n", "mnemonic": "RET"}, {"name": "Call far-away subroutine", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "auipc x1, offset[31 : 12] + offset[11]\njalr x1, offset[11:0](x1)\n", "mnemonic": "CALL"}, {"name": "Tail call far-away subroutine", "opcode": "", "encoding": "pseudo", "extension": "I", "long_description": "auipc x6, offset[31 : 12] + offset[11]\njalr x0, offset[11:0](x6)\n", "mnemonic": "TAIL"}, {"name": "Multiply", "opcode": "OP / MUL / MULDIV", "encoding": "R", "extension": "M", "long_description": "MUL performs an XLEN-bit\u00d7XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits\nin the destination register. MULH, MULHU, and MULHSU perform the same multiplication but re-\nturn the upper XLEN bits of the full 2\u00d7XLEN-bit product, for signed\u00d7signed, unsigned\u00d7unsigned,\nand signed rs1\u00d7unsigned rs2 multiplication, respectively. If both the high and low bits of the same\nproduct are required, then the recommended code sequence is: MULH[[S]U] rdh, rs1, rs2; MUL\nrdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be the same as rs1 or\nrs2). Microarchitectures can then fuse these into a single multiply operation instead of performing\ntwo separate multiplies.\n", "mnemonic": "MUL"}, {"name": "Multiply high", "opcode": "OP / MULH / MULDIV", "encoding": "R", "extension": "M", "long_description": "MUL performs an XLEN-bit\u00d7XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits\nin the destination register. MULH, MULHU, and MULHSU perform the same multiplication but re-\nturn the upper XLEN bits of the full 2\u00d7XLEN-bit product, for signed\u00d7signed, unsigned\u00d7unsigned,\nand signed rs1\u00d7unsigned rs2 multiplication, respectively. If both the high and low bits of the same\nproduct are required, then the recommended code sequence is: MULH[[S]U] rdh, rs1, rs2; MUL\nrdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be the same as rs1 or\nrs2). Microarchitectures can then fuse these into a single multiply operation instead of performing\ntwo separate multiplies.\n", "mnemonic": "MULH"}, {"name": "Multiply high unsigned", "opcode": "OP / MULHW / MULDIV", "encoding": "R", "extension": "M", "long_description": "MUL performs an XLEN-bit\u00d7XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits\nin the destination register. MULH, MULHU, and MULHSU perform the same multiplication but re-\nturn the upper XLEN bits of the full 2\u00d7XLEN-bit product, for signed\u00d7signed, unsigned\u00d7unsigned,\nand signed rs1\u00d7unsigned rs2 multiplication, respectively. If both the high and low bits of the same\nproduct are required, then the recommended code sequence is: MULH[[S]U] rdh, rs1, rs2; MUL\nrdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be the same as rs1 or\nrs2). Microarchitectures can then fuse these into a single multiply operation instead of performing\ntwo separate multiplies.\n", "mnemonic": "MULHU"}, {"name": "Multiply high signed-unsigned", "opcode": "OP / MULHSW / MULDIV", "encoding": "R", "extension": "M", "long_description": "MUL performs an XLEN-bit\u00d7XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits\nin the destination register. MULH, MULHU, and MULHSU perform the same multiplication but re-\nturn the upper XLEN bits of the full 2\u00d7XLEN-bit product, for signed\u00d7signed, unsigned\u00d7unsigned,\nand signed rs1\u00d7unsigned rs2 multiplication, respectively. If both the high and low bits of the same\nproduct are required, then the recommended code sequence is: MULH[[S]U] rdh, rs1, rs2; MUL\nrdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be the same as rs1 or\nrs2). Microarchitectures can then fuse these into a single multiply operation instead of performing\ntwo separate multiplies.\n", "mnemonic": "MULHSU"}, {"name": "Multiply word", "opcode": "OP-32 / MULW / MULDIV", "encoding": "R", "extension": "M", "long_description": "MULW is an RV64 instruction that multiplies the lower 32 bits of the source registers, placing the\nsign-extension of the lower 32 bits of the result into the destination register.\n", "mnemonic": "MULW"}, {"name": "Divide", "opcode": "OP / DIV / MULDIV", "encoding": "R", "extension": "M", "long_description": "DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by\nrs2, rounding towards zero. REM and REMU provide the remainder of the corresponding division\noperation. For REM, the sign of the result equals the sign of the dividend.\nFor both signed and unsigned division, it holds that dividend = divisor \u00d7 quotient + remainder.\nIf both the quotient and remainder are required from the same division, the recommended code\nsequence is: DIV[U] rdq, rs1, rs2; REM[U] rdr, rs1, rs2 (rdq cannot be the same as rs1 or rs2).\nMicroarchitectures can then fuse these into a single divide operation instead of performing two\nseparate divides.\n", "mnemonic": "DIV"}, {"name": "Divide unsigned", "opcode": "OP / DIVU / MULDIV", "encoding": "R", "extension": "M", "long_description": "DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by\nrs2, rounding towards zero. REM and REMU provide the remainder of the corresponding division\noperation. For REM, the sign of the result equals the sign of the dividend.\nFor both signed and unsigned division, it holds that dividend = divisor \u00d7 quotient + remainder.\nIf both the quotient and remainder are required from the same division, the recommended code\nsequence is: DIV[U] rdq, rs1, rs2; REM[U] rdr, rs1, rs2 (rdq cannot be the same as rs1 or rs2).\nMicroarchitectures can then fuse these into a single divide operation instead of performing two\nseparate divides.\n", "mnemonic": "DIVU"}, {"name": "Remainder", "opcode": "OP / REM / MULDIV", "encoding": "R", "extension": "M", "long_description": "DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by\nrs2, rounding towards zero. REM and REMU provide the remainder of the corresponding division\noperation. For REM, the sign of the result equals the sign of the dividend.\nFor both signed and unsigned division, it holds that dividend = divisor \u00d7 quotient + remainder.\nIf both the quotient and remainder are required from the same division, the recommended code\nsequence is: DIV[U] rdq, rs1, rs2; REM[U] rdr, rs1, rs2 (rdq cannot be the same as rs1 or rs2).\nMicroarchitectures can then fuse these into a single divide operation instead of performing two\nseparate divides.\n", "mnemonic": "REM"}, {"name": "Remainder unsigned", "opcode": "OP / REMU / MULDIV", "encoding": "R", "extension": "M", "long_description": "DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by\nrs2, rounding towards zero. REM and REMU provide the remainder of the corresponding division\noperation. For REM, the sign of the result equals the sign of the dividend.\nFor both signed and unsigned division, it holds that dividend = divisor \u00d7 quotient + remainder.\nIf both the quotient and remainder are required from the same division, the recommended code\nsequence is: DIV[U] rdq, rs1, rs2; REM[U] rdr, rs1, rs2 (rdq cannot be the same as rs1 or rs2).\nMicroarchitectures can then fuse these into a single divide operation instead of performing two\nseparate divides.\n", "mnemonic": "REMU"}, {"name": "Divide word", "opcode": "OP-32 / DIVW / MULDIV", "encoding": "R", "extension": "M", "long_description": "DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of rs1 by the lower 32\nbits of rs2, treating them as signed and unsigned integers respectively, placing the 32-bit quotient\nin rd, sign-extended to 64 bits. REMW and REMUW are RV64 instructions that provide the\ncorresponding signed and unsigned remainder operations respectively. Both REMW and REMUW\nalways sign-extend the 32-bit result to 64 bits, including on a divide by zero.\n", "mnemonic": "DIVW"}, {"name": "Divide word unsigned", "opcode": "OP-32 / DIVUW / MULDIV", "encoding": "R", "extension": "M", "long_description": "DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of rs1 by the lower 32\nbits of rs2, treating them as signed and unsigned integers respectively, placing the 32-bit quotient\nin rd, sign-extended to 64 bits. REMW and REMUW are RV64 instructions that provide the\ncorresponding signed and unsigned remainder operations respectively. Both REMW and REMUW\nalways sign-extend the 32-bit result to 64 bits, including on a divide by zero.\n", "mnemonic": "DIVUW"}, {"name": "Remainder word", "opcode": "OP-32 / REMW / MULDIV", "encoding": "R", "extension": "M", "long_description": "DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of rs1 by the lower 32\nbits of rs2, treating them as signed and unsigned integers respectively, placing the 32-bit quotient\nin rd, sign-extended to 64 bits. REMW and REMUW are RV64 instructions that provide the\ncorresponding signed and unsigned remainder operations respectively. Both REMW and REMUW\nalways sign-extend the 32-bit result to 64 bits, including on a divide by zero.\n", "mnemonic": "REMW"}, {"name": "Remainder word unsigned", "opcode": "OP-32 / REMUW / MULDIV", "encoding": "R", "extension": "M", "long_description": "DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of rs1 by the lower 32\nbits of rs2, treating them as signed and unsigned integers respectively, placing the 32-bit quotient\nin rd, sign-extended to 64 bits. REMW and REMUW are RV64 instructions that provide the\ncorresponding signed and unsigned remainder operations respectively. Both REMW and REMUW\nalways sign-extend the 32-bit result to 64 bits, including on a divide by zero.\n", "mnemonic": "REMUW"}, {"name": "Load reserved word", "opcode": "AMO / width / LR.W", "encoding": "R", "extension": "A", "long_description": "Complex atomic memory operations on a single memory word or doubleword are performed with the\nload-reserved (LR) and store-conditional (SC) instructions. LR.W loads a word from the address\nin rs1, places the sign-extended value in rd, and registers a reservation set\u2014a set of bytes that\nsubsumes the bytes in the addressed word. SC.W conditionally writes a word in rs2 to the address\nin rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the\nbytes being written. If the SC.W succeeds, the instruction writes the word in rs2 to memory, and\nit writes zero to rd. If the SC.W fails, the instruction does not write to memory, and it writes a\nnonzero value to rd. Regardless of success or failure, executing an SC.W instruction invalidates\nany reservation held by this hart. LR.D and SC.D act analogously on doublewords and are only\navailable on RV64. For RV64, LR.W and SC.W sign-extend the value placed in rd.\n", "mnemonic": "LR.W"}, {"name": "Load reserved doubleword", "opcode": "AMO / width / LR.D", "encoding": "R", "extension": "A", "long_description": "Complex atomic memory operations on a single memory word or doubleword are performed with the\nload-reserved (LR) and store-conditional (SC) instructions. LR.W loads a word from the address\nin rs1, places the sign-extended value in rd, and registers a reservation set\u2014a set of bytes that\nsubsumes the bytes in the addressed word. SC.W conditionally writes a word in rs2 to the address\nin rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the\nbytes being written. If the SC.W succeeds, the instruction writes the word in rs2 to memory, and\nit writes zero to rd. If the SC.W fails, the instruction does not write to memory, and it writes a\nnonzero value to rd. Regardless of success or failure, executing an SC.W instruction invalidates\nany reservation held by this hart. LR.D and SC.D act analogously on doublewords and are only\navailable on RV64. For RV64, LR.W and SC.W sign-extend the value placed in rd.\n", "mnemonic": "LR.D"}, {"name": "Store conditional word", "opcode": "AMO / width / SC.W", "encoding": "R", "extension": "A", "long_description": "Complex atomic memory operations on a single memory word or doubleword are performed with the\nload-reserved (LR) and store-conditional (SC) instructions. LR.W loads a word from the address\nin rs1, places the sign-extended value in rd, and registers a reservation set\u2014a set of bytes that\nsubsumes the bytes in the addressed word. SC.W conditionally writes a word in rs2 to the address\nin rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the\nbytes being written. If the SC.W succeeds, the instruction writes the word in rs2 to memory, and\nit writes zero to rd. If the SC.W fails, the instruction does not write to memory, and it writes a\nnonzero value to rd. Regardless of success or failure, executing an SC.W instruction invalidates\nany reservation held by this hart. LR.D and SC.D act analogously on doublewords and are only\navailable on RV64. For RV64, LR.W and SC.W sign-extend the value placed in rd.\n", "mnemonic": "SC.W"}, {"name": "Store conditional doubleword", "opcode": "AMO / width / SC.D", "encoding": "R", "extension": "A", "long_description": "Complex atomic memory operations on a single memory word or doubleword are performed with the\nload-reserved (LR) and store-conditional (SC) instructions. LR.W loads a word from the address\nin rs1, places the sign-extended value in rd, and registers a reservation set\u2014a set of bytes that\nsubsumes the bytes in the addressed word. SC.W conditionally writes a word in rs2 to the address\nin rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the\nbytes being written. If the SC.W succeeds, the instruction writes the word in rs2 to memory, and\nit writes zero to rd. If the SC.W fails, the instruction does not write to memory, and it writes a\nnonzero value to rd. Regardless of success or failure, executing an SC.W instruction invalidates\nany reservation held by this hart. LR.D and SC.D act analogously on doublewords and are only\navailable on RV64. For RV64, LR.W and SC.W sign-extend the value placed in rd.\n", "mnemonic": "SC.D"}, {"name": "Atomic swap word", "opcode": "AMO / width / AMOSWAP.W", "encoding": "R", "extension": "A", "long_description": "The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-\ntiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-\nstructions atomically load a data value from the address in rs1, place the value into register rd,\napply a binary operator to the loaded value and the original value in rs2, then store the result back\nto the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.\nFor RV64, 32-bit AMOs always sign-extend the value placed in rd.\n\nThe operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and\nsigned and unsigned integer maximum and minimum. Without ordering constraints, these AMOs\ncan be used to implement parallel reduction operations, where typically the return value would be\ndiscarded by writing to x0.\n", "mnemonic": "AMOSWAP.W"}, {"name": "Atomic swap doubleword", "opcode": "AMO / width / AMOSWAP.D", "encoding": "R", "extension": "A", "long_description": "The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-\ntiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-\nstructions atomically load a data value from the address in rs1, place the value into register rd,\napply a binary operator to the loaded value and the original value in rs2, then store the result back\nto the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.\nFor RV64, 32-bit AMOs always sign-extend the value placed in rd.\n\nThe operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and\nsigned and unsigned integer maximum and minimum. Without ordering constraints, these AMOs\ncan be used to implement parallel reduction operations, where typically the return value would be\ndiscarded by writing to x0.\n", "mnemonic": "AMOSWAP.D"}, {"name": "Atomic ADD word", "opcode": "AMO / width / AMOADD.W", "encoding": "R", "extension": "A", "long_description": "The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-\ntiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-\nstructions atomically load a data value from the address in rs1, place the value into register rd,\napply a binary operator to the loaded value and the original value in rs2, then store the result back\nto the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.\nFor RV64, 32-bit AMOs always sign-extend the value placed in rd.\n\nThe operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and\nsigned and unsigned integer maximum and minimum. Without ordering constraints, these AMOs\ncan be used to implement parallel reduction operations, where typically the return value would be\ndiscarded by writing to x0.\n", "mnemonic": "AMOADD.W"}, {"name": "Atomic ADD doubleword", "opcode": "AMO / width / AMOADD.D", "encoding": "R", "extension": "A", "long_description": "The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-\ntiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-\nstructions atomically load a data value from the address in rs1, place the value into register rd,\napply a binary operator to the loaded value and the original value in rs2, then store the result back\nto the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.\nFor RV64, 32-bit AMOs always sign-extend the value placed in rd.\n\nThe operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and\nsigned and unsigned integer maximum and minimum. Without ordering constraints, these AMOs\ncan be used to implement parallel reduction operations, where typically the return value would be\ndiscarded by writing to x0.\n", "mnemonic": "AMOADD.D"}, {"name": "Atomic AND word", "opcode": "AMO / width / AMOAND.W", "encoding": "R", "extension": "A", "long_description": "The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-\ntiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-\nstructions atomically load a data value from the address in rs1, place the value into register rd,\napply a binary operator to the loaded value and the original value in rs2, then store the result back\nto the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.\nFor RV64, 32-bit AMOs always sign-extend the value placed in rd.\n\nThe operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and\nsigned and unsigned integer maximum and minimum. Without ordering constraints, these AMOs\ncan be used to implement parallel reduction operations, where typically the return value would be\ndiscarded by writing to x0.\n", "mnemonic": "AMOAND.W"}, {"name": "Atomic AND doubleword", "opcode": "AMO / width / AMOAND.D", "encoding": "R", "extension": "A", "long_description": "The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-\ntiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-\nstructions atomically load a data value from the address in rs1, place the value into register rd,\napply a binary operator to the loaded value and the original value in rs2, then store the result back\nto the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.\nFor RV64, 32-bit AMOs always sign-extend the value placed in rd.\n\nThe operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and\nsigned and unsigned integer maximum and minimum. Without ordering constraints, these AMOs\ncan be used to implement parallel reduction operations, where typically the return value would be\ndiscarded by writing to x0.\n", "mnemonic": "AMOAND.D"}, {"name": "Atomic OR word", "opcode": "AMO / width / AMOOR.W", "encoding": "R", "extension": "A", "long_description": "The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-\ntiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-\nstructions atomically load a data value from the address in rs1, place the value into register rd,\napply a binary operator to the loaded value and the original value in rs2, then store the result back\nto the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.\nFor RV64, 32-bit AMOs always sign-extend the value placed in rd.\n\nThe operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and\nsigned and unsigned integer maximum and minimum. Without ordering constraints, these AMOs\ncan be used to implement parallel reduction operations, where typically the return value would be\ndiscarded by writing to x0.\n", "mnemonic": "AMOOR.W"}, {"name": "Atomic OR doubleword", "opcode": "AMO / width / AMOOR.D", "encoding": "R", "extension": "A", "long_description": "The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-\ntiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-\nstructions atomically load a data value from the address in rs1, place the value into register rd,\napply a binary operator to the loaded value and the original value in rs2, then store the result back\nto the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.\nFor RV64, 32-bit AMOs always sign-extend the value placed in rd.\n\nThe operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and\nsigned and unsigned integer maximum and minimum. Without ordering constraints, these AMOs\ncan be used to implement parallel reduction operations, where typically the return value would be\ndiscarded by writing to x0.\n", "mnemonic": "AMOOR.D"}, {"name": "Atomic XOR word", "opcode": "AMO / width / AMOXOR.W", "encoding": "R", "extension": "A", "long_description": "The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-\ntiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-\nstructions atomically load a data value from the address in rs1, place the value into register rd,\napply a binary operator to the loaded value and the original value in rs2, then store the result back\nto the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.\nFor RV64, 32-bit AMOs always sign-extend the value placed in rd.\n\nThe operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and\nsigned and unsigned integer maximum and minimum. Without ordering constraints, these AMOs\ncan be used to implement parallel reduction operations, where typically the return value would be\ndiscarded by writing to x0.\n", "mnemonic": "AMOXOR.W"}, {"name": "Atomic XOR doubleword", "opcode": "AMO / width / AMOXOR.D", "encoding": "R", "extension": "A", "long_description": "The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-\ntiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-\nstructions atomically load a data value from the address in rs1, place the value into register rd,\napply a binary operator to the loaded value and the original value in rs2, then store the result back\nto the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.\nFor RV64, 32-bit AMOs always sign-extend the value placed in rd.\n\nThe operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and\nsigned and unsigned integer maximum and minimum. Without ordering constraints, these AMOs\ncan be used to implement parallel reduction operations, where typically the return value would be\ndiscarded by writing to x0.\n", "mnemonic": "AMOXOR.D"}, {"name": "Atomic MAX word", "opcode": "AMO / width / AMOMAX.W", "encoding": "R", "extension": "A", "long_description": "The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-\ntiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-\nstructions atomically load a data value from the address in rs1, place the value into register rd,\napply a binary operator to the loaded value and the original value in rs2, then store the result back\nto the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.\nFor RV64, 32-bit AMOs always sign-extend the value placed in rd.\n\nThe operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and\nsigned and unsigned integer maximum and minimum. Without ordering constraints, these AMOs\ncan be used to implement parallel reduction operations, where typically the return value would be\ndiscarded by writing to x0.\n", "mnemonic": "AMOMAX.W"}, {"name": "Atomic MAX doubleword", "opcode": "AMO / width / AMOMAX.D", "encoding": "R", "extension": "A", "long_description": "The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-\ntiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-\nstructions atomically load a data value from the address in rs1, place the value into register rd,\napply a binary operator to the loaded value and the original value in rs2, then store the result back\nto the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.\nFor RV64, 32-bit AMOs always sign-extend the value placed in rd.\n\nThe operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and\nsigned and unsigned integer maximum and minimum. Without ordering constraints, these AMOs\ncan be used to implement parallel reduction operations, where typically the return value would be\ndiscarded by writing to x0.\n", "mnemonic": "AMOMAX.D"}, {"name": "Atomic MAXU word", "opcode": "AMO / width / AMOMAXU.W", "encoding": "R", "extension": "A", "long_description": "The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-\ntiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-\nstructions atomically load a data value from the address in rs1, place the value into register rd,\napply a binary operator to the loaded value and the original value in rs2, then store the result back\nto the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.\nFor RV64, 32-bit AMOs always sign-extend the value placed in rd.\n\nThe operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and\nsigned and unsigned integer maximum and minimum. Without ordering constraints, these AMOs\ncan be used to implement parallel reduction operations, where typically the return value would be\ndiscarded by writing to x0.\n", "mnemonic": "AMOMAXU.W"}, {"name": "Atomic MAXU doubleword", "opcode": "AMO / width / AMOMAXU.D", "encoding": "R", "extension": "A", "long_description": "The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-\ntiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-\nstructions atomically load a data value from the address in rs1, place the value into register rd,\napply a binary operator to the loaded value and the original value in rs2, then store the result back\nto the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.\nFor RV64, 32-bit AMOs always sign-extend the value placed in rd.\n\nThe operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and\nsigned and unsigned integer maximum and minimum. Without ordering constraints, these AMOs\ncan be used to implement parallel reduction operations, where typically the return value would be\ndiscarded by writing to x0.\n", "mnemonic": "AMOMAXU.D"}, {"name": "Atomic MIN word", "opcode": "AMO / width / AMOMIN.W", "encoding": "R", "extension": "A", "long_description": "The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-\ntiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-\nstructions atomically load a data value from the address in rs1, place the value into register rd,\napply a binary operator to the loaded value and the original value in rs2, then store the result back\nto the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.\nFor RV64, 32-bit AMOs always sign-extend the value placed in rd.\n\nThe operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and\nsigned and unsigned integer maximum and minimum. Without ordering constraints, these AMOs\ncan be used to implement parallel reduction operations, where typically the return value would be\ndiscarded by writing to x0.\n", "mnemonic": "AMOMIN.W"}, {"name": "Atomic MIN doubleword", "opcode": "AMO / width / AMOMIN.D", "encoding": "R", "extension": "A", "long_description": "The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-\ntiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-\nstructions atomically load a data value from the address in rs1, place the value into register rd,\napply a binary operator to the loaded value and the original value in rs2, then store the result back\nto the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.\nFor RV64, 32-bit AMOs always sign-extend the value placed in rd.\n\nThe operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and\nsigned and unsigned integer maximum and minimum. Without ordering constraints, these AMOs\ncan be used to implement parallel reduction operations, where typically the return value would be\ndiscarded by writing to x0.\n", "mnemonic": "AMOMIN.D"}, {"name": "Atomic MINU word", "opcode": "AMO / width / AMOMINU.W", "encoding": "R", "extension": "A", "long_description": "The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-\ntiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-\nstructions atomically load a data value from the address in rs1, place the value into register rd,\napply a binary operator to the loaded value and the original value in rs2, then store the result back\nto the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.\nFor RV64, 32-bit AMOs always sign-extend the value placed in rd.\n\nThe operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and\nsigned and unsigned integer maximum and minimum. Without ordering constraints, these AMOs\ncan be used to implement parallel reduction operations, where typically the return value would be\ndiscarded by writing to x0.\n", "mnemonic": "AMOMINU.W"}, {"name": "Atomic MINU doubleword", "opcode": "AMO / width / AMOMINU.D", "encoding": "R", "extension": "A", "long_description": "The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-\ntiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-\nstructions atomically load a data value from the address in rs1, place the value into register rd,\napply a binary operator to the loaded value and the original value in rs2, then store the result back\nto the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.\nFor RV64, 32-bit AMOs always sign-extend the value placed in rd.\n\nThe operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and\nsigned and unsigned integer maximum and minimum. Without ordering constraints, these AMOs\ncan be used to implement parallel reduction operations, where typically the return value would be\ndiscarded by writing to x0.\n", "mnemonic": "AMOMINU.D"}, {"name": "Floating point load word", "opcode": "LOAD-FP", "encoding": "I", "extension": "F", "long_description": "Floating-point loads and stores use the same base+offset addressing mode as the integer base ISA,\nwith a base address in register rs1 and a 12-bit signed byte offset. The FLW instruction loads\na single-precision floating-point value from memory into floating-point register rd. FSW stores a\nsingle-precision value from floating-point register rs2 to memory.\n", "mnemonic": "FLW"}, {"name": "Floating point store word", "opcode": "STORE-FP", "encoding": "I", "extension": "F", "long_description": "Floating-point loads and stores use the same base+offset addressing mode as the integer base ISA,\nwith a base address in register rs1 and a 12-bit signed byte offset. The FLW instruction loads\na single-precision floating-point value from memory into floating-point register rd. FSW stores a\nsingle-precision value from floating-point register rs2 to memory.\n", "mnemonic": "FSW"}, {"name": "Floating point add", "opcode": "OP-FP / FADD", "encoding": "R", "extension": "F", "long_description": "Floating-point arithmetic instructions with one or two source operands use the R-type format with\nthe OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition\n68\nand multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating-\npoint subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of\nrs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd.\n", "mnemonic": "FADD"}, {"name": "Floating point subtract", "opcode": "OP-FP / FSUB", "encoding": "R", "extension": "F", "long_description": "Floating-point arithmetic instructions with one or two source operands use the R-type format with\nthe OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition\n68\nand multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating-\npoint subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of\nrs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd.\n", "mnemonic": "FSUB"}, {"name": "Floating point multiply", "opcode": "OP-FP / FMUL", "encoding": "R", "extension": "F", "long_description": "Floating-point arithmetic instructions with one or two source operands use the R-type format with\nthe OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition\n68\nand multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating-\npoint subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of\nrs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd.\n", "mnemonic": "FMUL"}, {"name": "Floating point divide", "opcode": "OP-FP / FDIV", "encoding": "R", "extension": "F", "long_description": "Floating-point arithmetic instructions with one or two source operands use the R-type format with\nthe OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition\n68\nand multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating-\npoint subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of\nrs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd.\n", "mnemonic": "FDIV"}, {"name": "Floating point square root", "opcode": "OP-FP / FSQRT", "encoding": "R", "extension": "F", "long_description": "Floating-point arithmetic instructions with one or two source operands use the R-type format with\nthe OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition\n68\nand multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating-\npoint subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of\nrs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd.\n", "mnemonic": "FSQRT"}, {"name": "Floating point min", "opcode": "OP-FP / FMIN", "encoding": "R", "extension": "F", "long_description": "Floating-point arithmetic instructions with one or two source operands use the R-type format with\nthe OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition\n68\nand multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating-\npoint subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of\nrs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd.\n", "mnemonic": "FMIN"}, {"name": "Floating point max", "opcode": "OP-FP / F", "encoding": "R", "extension": "F", "long_description": "Floating-point arithmetic instructions with one or two source operands use the R-type format with\nthe OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition\n68\nand multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating-\npoint subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of\nrs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd.\n", "mnemonic": "FMAX"}, {"name": "Floating point fused multiply-add", "opcode": "FMADD", "encoding": "R4", "extension": "F", "long_description": "Floating-point fused multiply-add instructions require a new standard instruction format. R4-type\ninstructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This\nformat is only used by the floating-point fused multiply-add instructions.\nFMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to\nrd. FMADD.S computes (rs1\u00d7rs2)+rs3.\nFMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result\nto rd. FMSUB.S computes (rs1\u00d7rs2)-rs3.\nFNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and\nwrites the final result to rd. FNMSUB.S computes -(rs1\u00d7rs2)+rs3.\nFNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3,\nand writes the final result to rd. FNMADD.S computes -(rs1\u00d7rs2)-rs3.\n", "mnemonic": "FMADD"}, {"name": "Floating point fused multiply-subtract", "opcode": "FMSUB", "encoding": "R4", "extension": "F", "long_description": "Floating-point fused multiply-add instructions require a new standard instruction format. R4-type\ninstructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This\nformat is only used by the floating-point fused multiply-add instructions.\nFMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to\nrd. FMADD.S computes (rs1\u00d7rs2)+rs3.\nFMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result\nto rd. FMSUB.S computes (rs1\u00d7rs2)-rs3.\nFNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and\nwrites the final result to rd. FNMSUB.S computes -(rs1\u00d7rs2)+rs3.\nFNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3,\nand writes the final result to rd. FNMADD.S computes -(rs1\u00d7rs2)-rs3.\n", "mnemonic": "FMSUB"}, {"name": "Floating point fused negate multiply-add", "opcode": "FNMADD", "encoding": "R4", "extension": "F", "long_description": "Floating-point fused multiply-add instructions require a new standard instruction format. R4-type\ninstructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This\nformat is only used by the floating-point fused multiply-add instructions.\nFMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to\nrd. FMADD.S computes (rs1\u00d7rs2)+rs3.\nFMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result\nto rd. FMSUB.S computes (rs1\u00d7rs2)-rs3.\nFNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and\nwrites the final result to rd. FNMSUB.S computes -(rs1\u00d7rs2)+rs3.\nFNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3,\nand writes the final result to rd. FNMADD.S computes -(rs1\u00d7rs2)-rs3.\n", "mnemonic": "FNMADD"}, {"name": "Floating point fused negate multiply-subtract", "opcode": "FMNSUB", "encoding": "R4", "extension": "F", "long_description": "Floating-point fused multiply-add instructions require a new standard instruction format. R4-type\ninstructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This\nformat is only used by the floating-point fused multiply-add instructions.\nFMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to\nrd. FMADD.S computes (rs1\u00d7rs2)+rs3.\nFMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result\nto rd. FMSUB.S computes (rs1\u00d7rs2)-rs3.\nFNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and\nwrites the final result to rd. FNMSUB.S computes -(rs1\u00d7rs2)+rs3.\nFNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3,\nand writes the final result to rd. FNMADD.S computes -(rs1\u00d7rs2)-rs3.\n", "mnemonic": "FNMSUB"}, {"name": "Convert single floating point to word integer", "opcode": "OP-FP / FCVT", "encoding": "F", "extension": "F", "long_description": "Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the\nOP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-\npoint register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W\nor FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a\nfloating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and\nFCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S\nsign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U]\nare RV64-only instructions. If the rounded result is not representable in the destination format, it\nis clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs\nfor FCVT.int.S and the behavior for invalid inputs.\n\nAll floating-point to integer and integer to floating-point conversion instructions round according\nto the rm field. A floating-point register can be initialized to floating-point positive zero using\nFCVT.S.W rd, x0, which will never set any exception flags.\n", "mnemonic": "FCVT.W.S"}, {"name": "Convert single floating point to doubleword integer", "opcode": "OP-FP / FCVT", "encoding": "F", "extension": "F", "long_description": "Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the\nOP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-\npoint register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W\nor FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a\nfloating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and\nFCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S\nsign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U]\nare RV64-only instructions. If the rounded result is not representable in the destination format, it\nis clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs\nfor FCVT.int.S and the behavior for invalid inputs.\n\nAll floating-point to integer and integer to floating-point conversion instructions round according\nto the rm field. A floating-point register can be initialized to floating-point positive zero using\nFCVT.S.W rd, x0, which will never set any exception flags.\n", "mnemonic": "FCVT.L.S"}, {"name": "Convert single floating point to unsigned word integer", "opcode": "OP-FP / FCVT", "encoding": "F", "extension": "F", "long_description": "Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the\nOP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-\npoint register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W\nor FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a\nfloating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and\nFCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S\nsign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U]\nare RV64-only instructions. If the rounded result is not representable in the destination format, it\nis clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs\nfor FCVT.int.S and the behavior for invalid inputs.\n\nAll floating-point to integer and integer to floating-point conversion instructions round according\nto the rm field. A floating-point register can be initialized to floating-point positive zero using\nFCVT.S.W rd, x0, which will never set any exception flags.\n", "mnemonic": "FCVT.WU.S"}, {"name": "Convert single floating point to unsigned doubleword integer", "opcode": "OP-FP / FCVT", "encoding": "F", "extension": "F", "long_description": "Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the\nOP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-\npoint register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W\nor FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a\nfloating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and\nFCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S\nsign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U]\nare RV64-only instructions. If the rounded result is not representable in the destination format, it\nis clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs\nfor FCVT.int.S and the behavior for invalid inputs.\n\nAll floating-point to integer and integer to floating-point conversion instructions round according\nto the rm field. A floating-point register can be initialized to floating-point positive zero using\nFCVT.S.W rd, x0, which will never set any exception flags.\n", "mnemonic": "FCVT.LU.S"}, {"name": "Convert word integer to single floating point", "opcode": "OP-FP / FCVT", "encoding": "F", "extension": "F", "long_description": "Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the\nOP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-\npoint register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W\nor FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a\nfloating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and\nFCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S\nsign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U]\nare RV64-only instructions. If the rounded result is not representable in the destination format, it\nis clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs\nfor FCVT.int.S and the behavior for invalid inputs.\n\nAll floating-point to integer and integer to floating-point conversion instructions round according\nto the rm field. A floating-point register can be initialized to floating-point positive zero using\nFCVT.S.W rd, x0, which will never set any exception flags.\n", "mnemonic": "FCVT.S.W"}, {"name": "Convert double word integer to single floating point", "opcode": "OP-FP / FCVT", "encoding": "F", "extension": "F", "long_description": "Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the\nOP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-\npoint register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W\nor FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a\nfloating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and\nFCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S\nsign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U]\nare RV64-only instructions. If the rounded result is not representable in the destination format, it\nis clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs\nfor FCVT.int.S and the behavior for invalid inputs.\n\nAll floating-point to integer and integer to floating-point conversion instructions round according\nto the rm field. A floating-point register can be initialized to floating-point positive zero using\nFCVT.S.W rd, x0, which will never set any exception flags.\n", "mnemonic": "FCVT.S.L"}, {"name": "Convert unsigned word integer to single floating point", "opcode": "OP-FP / FCVT", "encoding": "F", "extension": "F", "long_description": "Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the\nOP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-\npoint register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W\nor FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a\nfloating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and\nFCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S\nsign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U]\nare RV64-only instructions. If the rounded result is not representable in the destination format, it\nis clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs\nfor FCVT.int.S and the behavior for invalid inputs.\n\nAll floating-point to integer and integer to floating-point conversion instructions round according\nto the rm field. A floating-point register can be initialized to floating-point positive zero using\nFCVT.S.W rd, x0, which will never set any exception flags.\n", "mnemonic": "FCVT.S.WU"}, {"name": "Convert unsigned double word integer to single floating point", "opcode": "OP-FP / FCVT", "encoding": "F", "extension": "F", "long_description": "Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the\nOP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-\npoint register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W\nor FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a\nfloating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and\nFCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S\nsign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U]\nare RV64-only instructions. If the rounded result is not representable in the destination format, it\nis clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs\nfor FCVT.int.S and the behavior for invalid inputs.\n\nAll floating-point to integer and integer to floating-point conversion instructions round according\nto the rm field. A floating-point register can be initialized to floating-point positive zero using\nFCVT.S.W rd, x0, which will never set any exception flags.\n", "mnemonic": "FCVT.S.LU"}, {"name": "Floating point sign injection", "opcode": "OP-FP / FSGNJ", "encoding": "R", "extension": "F", "long_description": "Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S,\nproduce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result\u2019s sign bit is\nrs2\u2019s sign bit; for FSGNJN, the result\u2019s sign bit is the opposite of rs2\u2019s sign bit; and for FSGNJX,\nthe sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set\nfloating-point exception flags, nor do they canonicalize NaNs. Note, FSGNJ.S rx, ry, ry moves ry\nto rx (assembler pseudoinstruction FMV.S rx, ry); FSGNJN.S rx, ry, ry moves the negation of ry\nto rx (assembler pseudoinstruction FNEG.S rx, ry); and FSGNJX.S rx, ry, ry moves the absolute\nvalue of ry to rx (assembler pseudoinstruction FABS.S rx, ry).\n", "mnemonic": "FSGNJ.S"}, {"name": "Floating point sign injection with negation", "opcode": "OP-FP / FSGNJ", "encoding": "R", "extension": "F", "long_description": "Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S,\nproduce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result\u2019s sign bit is\nrs2\u2019s sign bit; for FSGNJN, the result\u2019s sign bit is the opposite of rs2\u2019s sign bit; and for FSGNJX,\nthe sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set\nfloating-point exception flags, nor do they canonicalize NaNs. Note, FSGNJ.S rx, ry, ry moves ry\nto rx (assembler pseudoinstruction FMV.S rx, ry); FSGNJN.S rx, ry, ry moves the negation of ry\nto rx (assembler pseudoinstruction FNEG.S rx, ry); and FSGNJX.S rx, ry, ry moves the absolute\nvalue of ry to rx (assembler pseudoinstruction FABS.S rx, ry).\n", "mnemonic": "FSGNJN.S"}, {"name": "Floating point sign injection with SOR", "opcode": "OP-FP / FSGNJ", "encoding": "R", "extension": "F", "long_description": "Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S,\nproduce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result\u2019s sign bit is\nrs2\u2019s sign bit; for FSGNJN, the result\u2019s sign bit is the opposite of rs2\u2019s sign bit; and for FSGNJX,\nthe sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set\nfloating-point exception flags, nor do they canonicalize NaNs. Note, FSGNJ.S rx, ry, ry moves ry\nto rx (assembler pseudoinstruction FMV.S rx, ry); FSGNJN.S rx, ry, ry moves the negation of ry\nto rx (assembler pseudoinstruction FNEG.S rx, ry); and FSGNJX.S rx, ry, ry moves the absolute\nvalue of ry to rx (assembler pseudoinstruction FABS.S rx, ry).\n", "mnemonic": "FSGNJX.S"}, {"name": "Move single floating point to integer register", "opcode": "OP-FP / FMV.W.X", "encoding": "R", "extension": "F", "long_description": "Instructions are provided to move bit patterns between the floating-point and integer registers.\nFMV.X.W moves the single-precision value in floating-point register rs1 represented in IEEE 754-\n2008 encoding to the lower 32 bits of integer register rd. The bits are not modified in the transfer,\nand in particular, the payloads of non-canonical NaNs are preserved. For RV64, the higher 32 bits\nof the destination register are filled with copies of the floating-point number\u2019s sign bit.\nFMV.W.X moves the single-precision value encoded in IEEE 754-2008 standard encoding from the\nlower 32 bits of integer register rs1 to the floating-point register rd. The bits are not modified in\nthe transfer, and in particular, the payloads of non-canonical NaNs are preserved.\n", "mnemonic": "FMV.W.X"}, {"name": "Move word integer to single floating point register", "opcode": "OP-FP / FMV.X.W", "encoding": "R", "extension": "F", "long_description": "Instructions are provided to move bit patterns between the floating-point and integer registers.\nFMV.X.W moves the single-precision value in floating-point register rs1 represented in IEEE 754-\n2008 encoding to the lower 32 bits of integer register rd. The bits are not modified in the transfer,\nand in particular, the payloads of non-canonical NaNs are preserved. For RV64, the higher 32 bits\nof the destination register are filled with copies of the floating-point number\u2019s sign bit.\nFMV.W.X moves the single-precision value encoded in IEEE 754-2008 standard encoding from the\nlower 32 bits of integer register rs1 to the floating-point register rd. The bits are not modified in\nthe transfer, and in particular, the payloads of non-canonical NaNs are preserved.\n", "mnemonic": "FMV.X.W"}, {"name": "Floating point single precision equal", "opcode": "OP-FP / EQ / FCMP", "encoding": "R", "extension": "F", "long_description": "Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison be-\ntween floating-point registers (rs1 = rs2, rs1 < rs2, rs1 \u2264 rs2) writing 1 to the integer register rd\nif the condition holds, and 0 otherwise.\nFLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as signaling comparisons:\nthat is, they set the invalid operation exception flag if either input is NaN. FEQ.S performs a quiet\ncomparison: it only sets the invalid operation exception flag if either input is a signaling NaN. For\nall three instructions, the result is 0 if either operand is NaN.\n", "mnemonic": "FEQ.S"}, {"name": "Floating point single precision less than", "opcode": "OP-FP / LT / FCMP", "encoding": "R", "extension": "F", "long_description": "Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison be-\ntween floating-point registers (rs1 = rs2, rs1 < rs2, rs1 \u2264 rs2) writing 1 to the integer register rd\nif the condition holds, and 0 otherwise.\nFLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as signaling comparisons:\nthat is, they set the invalid operation exception flag if either input is NaN. FEQ.S performs a quiet\ncomparison: it only sets the invalid operation exception flag if either input is a signaling NaN. For\nall three instructions, the result is 0 if either operand is NaN.\n", "mnemonic": "FLT.S"}, {"name": "Floating point single precision less than or equal", "opcode": "OP-FP / LE / FCMP", "encoding": "R", "extension": "F", "long_description": "Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison be-\ntween floating-point registers (rs1 = rs2, rs1 < rs2, rs1 \u2264 rs2) writing 1 to the integer register rd\nif the condition holds, and 0 otherwise.\nFLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as signaling comparisons:\nthat is, they set the invalid operation exception flag if either input is NaN. FEQ.S performs a quiet\ncomparison: it only sets the invalid operation exception flag if either input is a signaling NaN. For\nall three instructions, the result is 0 if either operand is NaN.\n", "mnemonic": "FLE.S"}, {"name": "Floating point single precision classify", "opcode": "OP-FP / FCLASS", "encoding": "R", "extension": "F", "long_description": "The FCLASS.S instruction examines the value in floating-point register rs1 and writes to integer\nregister rd a 10-bit mask that indicates the class of the floating-point number. The format of the\nmask is described in Table 11.5. The corresponding bit in rd will be set if the property is true\nand clear otherwise. All other bits in rd are cleared. Note that exactly one bit in rd will be set.\nFCLASS.S does not set the floating-point exception flags.\n", "mnemonic": "FCLASS.S"}, {"name": "Copy single precision floating point register", "opcode": "", "encoding": "pseudo", "extension": "F", "long_description": "fsgnj.s rd, rs, rs\n", "mnemonic": "FMV.S"}, {"name": "Single precision absolute value", "opcode": "", "encoding": "pseudo", "extension": "F", "long_description": "fsgnjx.s rd, rs, rs\n", "mnemonic": "FABS.S"}, {"name": "Single precision negate", "opcode": "", "encoding": "pseudo", "extension": "F", "long_description": "fsgnjn.s rd, rs, rs\n", "mnemonic": "FNEG.S"}, {"name": "Copy double precision floating point register", "opcode": "", "encoding": "pseudo", "extension": "D", "long_description": "fsgnj.d rd, rs, rs\n", "mnemonic": "FMV.D"}, {"name": "Double precision absolute value", "opcode": "", "encoding": "pseudo", "extension": "F", "long_description": "fsgnjx.d rd, rs, rs\n", "mnemonic": "FABS.D"}, {"name": "Double precision negate", "opcode": "", "encoding": "pseudo", "extension": "F", "long_description": "fsgnjn.d rd, rs, rs\n", "mnemonic": "FNEG.D"}]
\ No newline at end of file
diff --git a/instructions.toml b/instructions.toml
new file mode 100644
index 0000000..a667fbc
--- /dev/null
+++ b/instructions.toml
@@ -0,0 +1,2092 @@
+[ADDI]
+name = "Add immediate"
+opcode = "OP-IMM / ADDI"
+encoding = "I"
+extension = "I"
+long_description = """
+ADDI adds the sign-extended 12-bit immediate to register rs1. Arithmetic overflow is ignored and
+the result is simply the low XLEN bits of the result. ADDI rd, rs1, 0 is used to implement the MV
+rd, rs1 assembler pseudoinstruction.
+"""
+
+
+[SLTI]
+name = "Set less than immediate"
+opcode = "OP-IMM / SLTI"
+encoding = "I"
+extension = "I"
+long_description = """
+SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the signextended immediate when both are treated as signed numbers, else 0 is written to rd. SLTIU is
+similar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to
+XLEN bits then treated as an unsigned number). Note, SLTIU rd, rs1, 1 sets rd to 1 if rs1 equals
+zero, otherwise sets rd to 0 (assembler pseudoinstruction SEQZ rd, rs)
+"""
+
+
+[SLTIU]
+name = "Set less than immediate unsigned"
+opcode = "OP-IMM / SLTIU"
+encoding = "I"
+extension = "I"
+long_description = """
+SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the signextended immediate when both are treated as signed numbers, else 0 is written to rd. SLTIU is
+similar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to
+XLEN bits then treated as an unsigned number). Note, SLTIU rd, rs1, 1 sets rd to 1 if rs1 equals
+zero, otherwise sets rd to 0 (assembler pseudoinstruction SEQZ rd, rs)
+"""
+
+[ANDI]
+name = "AND immediate"
+opcode = "OP-IMM / ANDI"
+encoding = "I"
+extension = "I"
+long_description = """
+ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1
+and the sign-extended 12-bit immediate and place the result in rd. Note, XORI rd, rs1, -1 performs
+a bitwise logical inversion of register rs1 (assembler pseudoinstruction
+NOT rd, rs).
+"""
+
+[ORI]
+name = "OR immediate"
+opcode = "OP-IMM / ORI"
+encoding = "I"
+extension = "I"
+long_description = """
+ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1
+and the sign-extended 12-bit immediate and place the result in rd. Note, XORI rd, rs1, -1 performs
+a bitwise logical inversion of register rs1 (assembler pseudoinstruction
+NOT rd, rs).
+"""
+
+[XORI]
+name = "XOR immediate"
+opcode = "OP-IMM / XORI"
+encoding = "I"
+extension = "I"
+long_description = """
+ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1
+and the sign-extended 12-bit immediate and place the result in rd. Note, XORI rd, rs1, -1 performs
+a bitwise logical inversion of register rs1 (assembler pseudoinstruction
+NOT rd, rs).
+"""
+
+[SLLI]
+name = "Shift left logical immediate"
+opcode = "OP-IMM / SLLI"
+encoding = "I"
+extension = "I"
+long_description = """
+Shifts by a constant are encoded as a specialization of the I-type
+format.  The operand to be shiftedis inrs1, and the shift amount is
+encoded in the lower 5 bits of the I-immediate field.  The rightshift
+type is encoded in bit 30.  SLLI is a logical left shift (zeros are
+shifted into the lower bits); SRLI is a logical right shift (zeros are
+shifted into the upper bits); and SRAI is an arithmetic rightshift (the
+original sign bit is copied into the vacated upper bits).
+"""
+
+[SRLI]
+name = "Shift right logical immediate"
+opcode = "OP-IMM / SRLI"
+encoding = "I"
+extension = "I"
+long_description = """
+Shifts by a constant are encoded as a specialization of the I-type
+format.  The operand to be shiftedis inrs1, and the shift amount is
+encoded in the lower 5 bits of the I-immediate field.  The rightshift
+type is encoded in bit 30.  SLLI is a logical left shift (zeros are
+shifted into the lower bits); SRLI is a logical right shift (zeros are
+shifted into the upper bits); and SRAI is an arithmetic rightshift (the
+original sign bit is copied into the vacated upper bits).
+"""
+
+[SRAI]
+name="Shift right arithmetic immediate"
+opcode = "OP-IMM / SRAI"
+encoding = "I"
+extension = "I"
+long_description = """
+Shifts by a constant are encoded as a specialization of the I-type
+format.  The operand to be shiftedis inrs1, and the shift amount is
+encoded in the lower 5 bits of the I-immediate field.  The rightshift
+type is encoded in bit 30.  SLLI is a logical left shift (zeros are
+shifted into the lower bits); SRLI is a logical right shift (zeros are
+shifted into the upper bits); and SRAI is an arithmetic rightshift (the
+original sign bit is copied into the vacated upper bits).
+"""
+
+[LUI]
+name = "Load upper immediate"
+opcode = "LUI"
+encoding = "U"
+extension = "I"
+long_description = """
+LUI (load upper immediate) is used to build 32-bit constants and uses the U-type format.  LUIplaces the U-immediate value in the top 20 bits of the destination registerrd, filling in the lowest12 bits with zeros.
+"""
+
+[AUIPC]
+name = "Add upper immediate to PC"
+opcode = "AUIPC"
+encoding = "U"
+extension = "I"
+long_description = """
+AUIPC (add upper immediate topc) is used to buildpc-relative addresses and uses the U-typeformat.  AUIPC forms a 32-bit offset from the 20-bit U-immediate, filling in the lowest 12 bits withzeros, adds this offset to the address of the AUIPC instruction, then places the result in registerrd.
+"""
+
+[ADD]
+name = "Add"
+opcode = "OP / ADD / 0"
+encoding = "R"
+extension = "I"
+long_description = """
+ADD performs the addition of rs 1andrs2. SUB performs the subtraction of rs2 from rs1. Overflow sare ignored and the low XLEN bits of results are written to the destination rd.
+"""
+
+
+[SUB]
+name = "SUB"
+opcode = "OP / SUB / 0b0100000"
+encoding = "R"
+extension = "I"
+long_description = """
+ADD performs the addition of rs 1andrs2. SUB performs the subtraction of rs2 from rs1. Overflow sare ignored and the low XLEN bits of results are written to the destination rd.
+"""
+
+[SLT]
+name = "Signed less than compare"
+opcode = "OP / SLT / 0"
+encoding = "R"
+extension = "I"
+long_description = """
+SLT and SLTU perform signed and unsigned compares respectively, writing 1 tordifrs1<rs2, 0 otherwise.  Note,
+SLTU rd,x0,rs2 sets rd to  1  if rs2 is  not  equal  to  zero,  otherwise  sets rd to  zero  (assembler pseudoinstruction SNEZ rd, rs).
+"""
+
+[SLTU]
+name = "Signed less than compare unsigned"
+opcode = "OP / SLTU / 0"
+encoding = "R"
+extension = "I"
+long_description = """
+SLT and SLTU perform signed and unsigned compares respectively, writing 1 tordifrs1<rs2, 0 otherwise.  Note,
+SLTU rd,x0,rs2 sets rd to  1  if rs2 is  not  equal  to  zero,  otherwise  sets rd to  zero  (assembler pseudoinstruction SNEZ rd, rs).
+"""
+
+[AND]
+name = "AND"
+opcode = "OP / AND / 0"
+encoding = "R"
+extension = "I"
+long_description = """
+AND, OR, and XOR perform bitwise logical operations.
+"""
+
+[OR]
+name = "OR"
+opcode = "OP / OR / 0"
+encoding = "R"
+extension = "I"
+long_description = """
+AND, OR, and XOR perform bitwise logical operations.
+"""
+
+[XOR]
+name = "XOR"
+opcode = "OP / XOR / 0"
+encoding = "R"
+extension = "I"
+long_description = """
+AND, OR, and XOR perform bitwise logical operations.
+"""
+
+[SLL]
+name = "Shift left logical"
+opcode = "OP / SLL / 0"
+encoding = "R"
+extension = "I"
+long_description = """
+SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value inregister rs1 by the shift amount held in the lower 5 bits of register rs2
+"""
+
+[SRL]
+name = "Shift right logical"
+opcode = "OP / SRL / 0"
+encoding = "R"
+extension = "I"
+long_description = """
+SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value inregister rs1 by the shift amount held in the lower 5 bits of register rs2
+"""
+
+[SRA]
+name = "Shift right arithmetic"
+opcode = "OP / SRA / 0b0100000"
+encoding = "R"
+extension = "I"
+long_description = """
+SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value inregister rs1 by the shift amount held in the lower 5 bits of register rs2
+"""
+
+[NOP]
+name = "No operation"
+opcode = "OP-IMM / ADDI"
+encoding = "I"
+extension = "I"
+long_description = """
+The NOP instruction does not change any architecturally visible state, except for advancing the pc and incrementing any applicable performance counters.  NOP is encoded as ADDI x0, x0, 0.
+"""
+
+[J]
+name = "Unconditional jump"
+opcode = "JAL"
+encoding = "J"
+extension = "I"
+long_description = """
+Plain unconditional jumps (assembler pseudoinstruction J) are encoded as
+a JAL with rd=x0.
+"""
+
+[JAL]
+name = "Jump and link"
+opcode = "JAL"
+encoding = "J"
+extension = "I"
+long_description = """
+The  jump  and  link  (JAL)  instruction  uses  the  J-type  format,  where  the  J-immediate  encodes  asigned offset in multiples of 2 bytes.  The offset is sign-extended and added to the address of thejump instruction to form the jump target address.  Jumps can therefore target a±1 MiB range.  JAL stores the address of the instruction following the jump (pc+4) into register rd.  The standard software calling convention uses x1 as the return address register and x5 as an alternate link register
+"""
+
+[JALR]
+name = "Jump and link register"
+opcode = "JAL"
+encoding = "I"
+extension = "I"
+long_description = """
+The indirect jump instruction JALR (jump and link register) uses the I-type encoding. The target
+address is obtained by adding the sign-extended 12-bit I-immediate to the register rs1, then setting
+the least-significant bit of the result to zero. The address of the instruction following the jump
+(pc+4) is written to register rd. Register x0 can be used as the destination if the result is not
+required.
+"""
+
+[BEQ]
+name = "Branch if equal"
+opcode = "BRANCH / BEQ"
+encoding = "B"
+extension = "I"
+long_description = """
+Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2
+are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using
+signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater
+than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU,
+BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU,
+respectively
+"""
+
+
+[BNE]
+name = "Branch if not equal"
+opcode = "BRANCH / BNE"
+encoding = "B"
+extension = "I"
+long_description = """
+Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2
+are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using
+signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater
+than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU,
+BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU,
+respectively
+"""
+
+[BLT]
+name = "Branch if less than"
+opcode = "BRANCH / BLT"
+encoding = "B"
+extension = "I"
+long_description = """
+Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2
+are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using
+signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater
+than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU,
+BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU,
+respectively
+"""
+
+[BLTU]
+name = "Branch if less than unsigned"
+opcode = "BRANCH / BLTU"
+encoding = "B"
+extension = "I"
+long_description = """
+Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2
+are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using
+signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater
+than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU,
+BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU,
+respectively
+"""
+
+[BGE]
+name = "Branch if greater or equal"
+opcode = "BRANCH / BGE"
+encoding = "B"
+extension = "I"
+long_description = """
+Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2
+are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using
+signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater
+than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU,
+BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU,
+respectively
+"""
+
+[BGEU]
+name = "Branch if greater or equal unsigned"
+opcode = "BRANCH / BGEU"
+encoding = "B"
+extension = "I"
+long_description = """
+Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2
+are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using
+signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater
+than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU,
+BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU,
+respectively
+"""
+
+[LW]
+name = "Load word"
+opcode = "LOAD / width"
+encoding = "I"
+extension = "I"
+long_description = """
+The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory,
+then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then
+zero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values.
+"""
+
+[LH]
+name = "Load half word"
+opcode = "LOAD / width"
+encoding = "I"
+extension = "I"
+long_description = """
+The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory,
+then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then
+zero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values.
+"""
+
+[LHU]
+name = "Load half word unsigned"
+opcode = "LOAD / width"
+encoding = "I"
+extension = "I"
+long_description = """
+The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory,
+then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then
+zero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values.
+"""
+
+[LB]
+name = "Load byte"
+opcode = "LOAD / width"
+encoding = "I"
+extension = "I"
+long_description = """
+The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory,
+then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then
+zero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values.
+"""
+
+[LBU]
+name = "Load byte unsigned"
+opcode = "LOAD / width"
+encoding = "I"
+extension = "I"
+long_description = """
+The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory,
+then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then
+zero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values.
+"""
+
+
+[SW]
+name = "Store word"
+opcode = "STORE / width"
+encoding = "S"
+extension = "I"
+long_description = """
+The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register
+rs2 to memory
+"""
+
+[SH]
+name = "Store half word"
+opcode = "STORE / width"
+encoding = "S"
+extension = "I"
+long_description = """
+The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register
+rs2 to memory
+"""
+
+[SB]
+name = "Store byte"
+opcode = "STORE / width"
+encoding = "S"
+extension = "I"
+long_description = """
+The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register
+rs2 to memory
+"""
+
+[FENCE]
+name = "Fence"
+opcode = "MISC-MEM / FENCE"
+encoding = "I"
+extension = "I"
+long_description = """
+The FENCE instruction is used to order device I/O and memory accesses as
+viewed by other RISCV harts and external devices or coprocessors. Any
+combination of device input (I), device output (O), memory reads (R),
+and memory writes (W) may be ordered with respect to any combination of
+the same. Informally, no other RISC-V hart or external device can
+observe any operation in the successor set following a FENCE before any
+operation in the predecessor set preceding the FENCE. Chapter 14
+provides a precise description of the RISC-V memory consistency model
+"""
+
+[ECALL]
+name = "Environment call"
+opcode = "SYSTEM / PRIV / ECALL"
+encoding = "I"
+extension = "I"
+long_description = """
+The ECALL instruction is used to make a service request to the execution environment. The EEI
+will define how parameters for the service request are passed, but usually these will be in defined
+locations in the integer register file
+"""
+
+[EBREAK]
+name = "Environment break point"
+opcode = "SYSTEM / PRIV / EBREAK"
+encoding = "I"
+extension = "I"
+long_description = """
+The EBREAK instruction is used to return control to a debugging environment.
+"""
+
+[HINT]
+name = "Hint"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+RV32I reserves a large encoding space for HINT instructions, which are usually used to communicate performance hints to the microarchitecture. HINTs are encoded as integer computational
+instructions with rd=x0. Hence, like the NOP instruction, HINTs do not change any architecturally
+visible state, except for advancing the pc and any applicable performance counters. Implementations are always allowed to ignore the encoded hints.
+"""
+
+["FENCE.I"]
+name = "Fence"
+opcode = "MISC-MEM / FENCE.I"
+encoding = "I"
+extension = "Zifencei"
+long_description = """
+The FENCE.I instruction is used to synchronize the instruction and data streams. RISC-V does
+not guarantee that stores to instruction memory will be made visible to instruction fetches on a
+RISC-V hart until that hart executes a FENCE.I instruction. A FENCE.I instruction ensures that
+a subsequent instruction fetch on a RISC-V hart will see any previous data stores already visible to
+the same RISC-V hart. FENCE.I does not ensure that other RISC-V harts’ instruction fetches will
+observe the local hart’s stores in a multiprocessor system. To make a store to instruction memory
+visible to all RISC-V harts, the writing hart has to execute a data FENCE before requesting that
+all remote RISC-V harts execute a FENCE.I.
+
+The unused fields in the FENCE.I instruction, imm[11:0], rs1, and rd, are reserved for finer-grain
+fences in future extensions. For forward compatibility, base implementations shall ignore these
+fields, and standard software shall zero these fields.
+"""
+
+[ADDIW]
+name = "Add immediate word"
+opcode = "OP-IMM-32 / ADDIW"
+encoding = "I"
+extension = "I"
+long_description = """
+ADDIW is an RV64I instruction that adds the sign-extended 12-bit immediate to register rs1
+and produces the proper sign-extension of a 32-bit result in rd. Overflows are ignored and the
+result is the low 32 bits of the result sign-extended to 64 bits. Note, ADDIW rd, rs1, 0 writes
+the sign-extension of the lower 32 bits of register rs1 into register rd (assembler pseudoinstruction
+SEXT.W)
+"""
+
+[SLLIW]
+name = "Shift left logical immediate word"
+opcode = "OP-IMM-32 / SLLIW"
+encoding = "I"
+extension = "I"
+long_description = """
+SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate
+on 32-bit values and produce signed 32-bit results. SLLIW, SRLIW, and SRAIW encodings with
+imm[5] ̸= 0 are reserved.
+"""
+
+[SRLIW]
+name = "Shift right logical immediate word"
+opcode = "OP-IMM-32 / SLLIW"
+encoding = "I"
+extension = "I"
+long_description = """
+SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate
+on 32-bit values and produce signed 32-bit results. SLLIW, SRLIW, and SRAIW encodings with
+imm[5] ̸= 0 are reserved.
+"""
+
+
+[SRAIW]
+name = "Shift right arithmetic immediate word"
+opcode = "OP-IMM-32 / SRAIW"
+encoding = "I"
+extension = "I"
+long_description = """
+SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate
+on 32-bit values and produce signed 32-bit results. SLLIW, SRLIW, and SRAIW encodings with
+imm[5] ̸= 0 are reserved.
+"""
+
+[ADDW]
+name = "Add word"
+opcode = "OP-32 / ADDW"
+encoding = "R"
+extension = "I"
+long_description = """
+ADDW and SUBW are RV64I-only instructions that are defined analogously to ADD and SUB
+but operate on 32-bit values and produce signed 32-bit results. Overflows are ignored, and the low
+32-bits of the result is sign-extended to 64-bits and written to the destination register
+"""
+
+[SUBW]
+name = "Subtract word"
+opcode = "OP-32 / SUBW"
+encoding = "R"
+extension = "I"
+long_description = """
+ADDW and SUBW are RV64I-only instructions that are defined analogously to ADD and SUB
+but operate on 32-bit values and produce signed 32-bit results. Overflows are ignored, and the low
+32-bits of the result is sign-extended to 64-bits and written to the destination register
+"""
+
+[SLLW]
+name = "Shift left logical word"
+opcode = "OP-32 / SLLW"
+encoding = "R"
+extension = "I"
+long_description = """
+SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate
+on 32-bit values and produce signed 32-bit results. The shift amount is given by rs2[4:0]
+"""
+
+[SRLW]
+name = "Shift right logical word"
+opcode = "OP-32 / SRLW"
+encoding = "R"
+extension = "I"
+long_description = """
+SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate
+on 32-bit values and produce signed 32-bit results. The shift amount is given by rs2[4:0]
+"""
+
+[SRAW]
+name = "Shift right arithmetic word"
+opcode = "OP-32 / SRAW"
+encoding = "R"
+extension = "I"
+long_description = """
+SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate
+on 32-bit values and produce signed 32-bit results. The shift amount is given by rs2[4:0]
+"""
+
+[LA]
+name = "Load absolute address"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+Load absolute address, where delta = symbol − pc.
+
+Non-position-independent version:
+auipc rd, delta[31 : 12] + delta[11]
+addi rd, rd, delta[11:0]
+
+Position-independent version:
+auipc rd, delta[31 : 12] + delta[11]
+l{w|d} rd, rd, delta[11:0]
+
+"""
+
+[LLA]
+name = "Load local address"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+Load local address, where delta = symbol − pc
+
+auipc rd, delta[31 : 12] + delta[11]
+addi rd, rd, delta[11:0]
+"""
+
+["LB/LH/LW/LD"]
+name = "Load global byte/halfword/word/double"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+Load global
+
+auipc rd, delta[31 : 12] + delta[11]
+l{b|h|w|d} rd, delta[11:0](rd)
+"""
+
+["SB/SH/SW/SD"]
+name = "Store global byte/halfword/word/double"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+Store global
+
+auipc rt, delta[31 : 12] + delta[11]
+s{b|h|w|d} rd, delta[11:0](rt)
+"""
+
+[LI]
+name = "Load immediate"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+Load immediate.  Expands to "myriad sequences".
+"""
+
+[MV]
+name = "Move"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+Copy register
+
+add rd, rs, 0
+"""
+
+[NOT]
+name = "One's complement negate"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+One's complement negation.
+
+xori rd, rs, -1
+"""
+
+[NEG]
+name = "Two's complement negate"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+Two's complement negation.
+
+sub rd, x0, rs
+"""
+
+[NEGW]
+name = "Two's complement negate word"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+Two's complement negation, word length.
+
+subw rd, x0, rs
+"""
+
+
+["SEXT.W"]
+name = "Sign extend word"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+Sign extend word
+
+addiw rd, rs, 0
+"""
+
+[SEQZ]
+name = "Set if equal to zero"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+sltiu rd, rs, 1
+"""
+
+[SNEZ]
+name = "Set if not equal zero"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+sltu rd, x0, rs
+"""
+
+[SLTZ]
+name = "Set if less than zero"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+slt rd, rs, x0
+"""
+
+
+[SGTZ]
+name = "Set if greater than zero"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+lst rd, x0, rs
+"""
+
+[BEQZ]
+name = "Branch if equal to zero"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+beq rs, x0, offset
+"""
+
+[BNEZ]
+name = "Branch if not equal zero"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+bne rs, x0, offset
+"""
+
+[BLEZ]
+name = "Branch if less than zero"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+bge x0, rs, offset
+"""
+
+
+[BGEZ]
+name = "Branch if greater or equal to zero"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+bge rs, x0, offset
+"""
+
+[BLTZ]
+name = "Branch if less than zero"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+blt rs, x0, offset
+"""
+
+[BGTZ]
+name = "Branch if greater than zero"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+blt x0, rs, offset
+"""
+
+[BTG]
+name = "Branch if greater than"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+blt rt, rs, offset
+"""
+
+
+[BLE]
+name = "Branch if less than or equal"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+bge rt, rs, offset
+"""
+
+[BGTU]
+name = "Branch if greater than, unsigned"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+bltu rt, rs, offset
+"""
+
+[BLEU]
+name = "Branch if less than, unsigned"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+bgeu rt, rs, offset
+"""
+
+[JR]
+name = "Jump register"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+jalr x0, 0(rs)
+"""
+
+
+[RET]
+name = "Return from subroutine"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+jalr x0, 0(x1)
+"""
+
+[CALL]
+name = "Call far-away subroutine"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+auipc x1, offset[31 : 12] + offset[11]
+jalr x1, offset[11:0](x1)
+"""
+
+[TAIL]
+name = "Tail call far-away subroutine"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+long_description = """
+auipc x6, offset[31 : 12] + offset[11]
+jalr x0, offset[11:0](x6)
+"""
+
+[MUL]
+name = "Multiply"
+opcode = "OP / MUL / MULDIV"
+encoding = "R"
+extension = "M"
+long_description = """
+MUL performs an XLEN-bit×XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits
+in the destination register. MULH, MULHU, and MULHSU perform the same multiplication but re-
+turn the upper XLEN bits of the full 2×XLEN-bit product, for signed×signed, unsigned×unsigned,
+and signed rs1×unsigned rs2 multiplication, respectively. If both the high and low bits of the same
+product are required, then the recommended code sequence is: MULH[[S]U] rdh, rs1, rs2; MUL
+rdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be the same as rs1 or
+rs2). Microarchitectures can then fuse these into a single multiply operation instead of performing
+two separate multiplies.
+"""
+
+
+[MULH]
+name = "Multiply high"
+opcode = "OP / MULH / MULDIV"
+encoding = "R"
+extension = "M"
+long_description = """
+MUL performs an XLEN-bit×XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits
+in the destination register. MULH, MULHU, and MULHSU perform the same multiplication but re-
+turn the upper XLEN bits of the full 2×XLEN-bit product, for signed×signed, unsigned×unsigned,
+and signed rs1×unsigned rs2 multiplication, respectively. If both the high and low bits of the same
+product are required, then the recommended code sequence is: MULH[[S]U] rdh, rs1, rs2; MUL
+rdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be the same as rs1 or
+rs2). Microarchitectures can then fuse these into a single multiply operation instead of performing
+two separate multiplies.
+"""
+
+
+[MULHU]
+name = "Multiply high unsigned"
+opcode = "OP / MULHW / MULDIV"
+encoding = "R"
+extension = "M"
+long_description = """
+MUL performs an XLEN-bit×XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits
+in the destination register. MULH, MULHU, and MULHSU perform the same multiplication but re-
+turn the upper XLEN bits of the full 2×XLEN-bit product, for signed×signed, unsigned×unsigned,
+and signed rs1×unsigned rs2 multiplication, respectively. If both the high and low bits of the same
+product are required, then the recommended code sequence is: MULH[[S]U] rdh, rs1, rs2; MUL
+rdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be the same as rs1 or
+rs2). Microarchitectures can then fuse these into a single multiply operation instead of performing
+two separate multiplies.
+"""
+
+
+[MULHSU]
+name = "Multiply high signed-unsigned"
+opcode = "OP / MULHSW / MULDIV"
+encoding = "R"
+extension = "M"
+long_description = """
+MUL performs an XLEN-bit×XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits
+in the destination register. MULH, MULHU, and MULHSU perform the same multiplication but re-
+turn the upper XLEN bits of the full 2×XLEN-bit product, for signed×signed, unsigned×unsigned,
+and signed rs1×unsigned rs2 multiplication, respectively. If both the high and low bits of the same
+product are required, then the recommended code sequence is: MULH[[S]U] rdh, rs1, rs2; MUL
+rdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be the same as rs1 or
+rs2). Microarchitectures can then fuse these into a single multiply operation instead of performing
+two separate multiplies.
+"""
+
+
+[MULW]
+name = "Multiply word"
+opcode = "OP-32 / MULW / MULDIV"
+encoding = "R"
+extension = "M"
+long_description = """
+MULW is an RV64 instruction that multiplies the lower 32 bits of the source registers, placing the
+sign-extension of the lower 32 bits of the result into the destination register.
+"""
+
+
+[DIV]
+name = "Divide"
+opcode = "OP / DIV / MULDIV"
+encoding = "R"
+extension = "M"
+long_description = """
+DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by
+rs2, rounding towards zero. REM and REMU provide the remainder of the corresponding division
+operation. For REM, the sign of the result equals the sign of the dividend.
+For both signed and unsigned division, it holds that dividend = divisor × quotient + remainder.
+If both the quotient and remainder are required from the same division, the recommended code
+sequence is: DIV[U] rdq, rs1, rs2; REM[U] rdr, rs1, rs2 (rdq cannot be the same as rs1 or rs2).
+Microarchitectures can then fuse these into a single divide operation instead of performing two
+separate divides.
+"""
+
+[DIVU]
+name = "Divide unsigned"
+opcode = "OP / DIVU / MULDIV"
+encoding = "R"
+extension = "M"
+long_description = """
+DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by
+rs2, rounding towards zero. REM and REMU provide the remainder of the corresponding division
+operation. For REM, the sign of the result equals the sign of the dividend.
+For both signed and unsigned division, it holds that dividend = divisor × quotient + remainder.
+If both the quotient and remainder are required from the same division, the recommended code
+sequence is: DIV[U] rdq, rs1, rs2; REM[U] rdr, rs1, rs2 (rdq cannot be the same as rs1 or rs2).
+Microarchitectures can then fuse these into a single divide operation instead of performing two
+separate divides.
+"""
+
+[REM]
+name = "Remainder"
+opcode = "OP / REM / MULDIV"
+encoding = "R"
+extension = "M"
+long_description = """
+DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by
+rs2, rounding towards zero. REM and REMU provide the remainder of the corresponding division
+operation. For REM, the sign of the result equals the sign of the dividend.
+For both signed and unsigned division, it holds that dividend = divisor × quotient + remainder.
+If both the quotient and remainder are required from the same division, the recommended code
+sequence is: DIV[U] rdq, rs1, rs2; REM[U] rdr, rs1, rs2 (rdq cannot be the same as rs1 or rs2).
+Microarchitectures can then fuse these into a single divide operation instead of performing two
+separate divides.
+"""
+
+[REMU]
+name = "Remainder unsigned"
+opcode = "OP / REMU / MULDIV"
+encoding = "R"
+extension = "M"
+long_description = """
+DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by
+rs2, rounding towards zero. REM and REMU provide the remainder of the corresponding division
+operation. For REM, the sign of the result equals the sign of the dividend.
+For both signed and unsigned division, it holds that dividend = divisor × quotient + remainder.
+If both the quotient and remainder are required from the same division, the recommended code
+sequence is: DIV[U] rdq, rs1, rs2; REM[U] rdr, rs1, rs2 (rdq cannot be the same as rs1 or rs2).
+Microarchitectures can then fuse these into a single divide operation instead of performing two
+separate divides.
+"""
+
+[DIVW]
+name = "Divide word"
+opcode = "OP-32 / DIVW / MULDIV"
+encoding = "R"
+extension = "M"
+long_description = """
+DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of rs1 by the lower 32
+bits of rs2, treating them as signed and unsigned integers respectively, placing the 32-bit quotient
+in rd, sign-extended to 64 bits. REMW and REMUW are RV64 instructions that provide the
+corresponding signed and unsigned remainder operations respectively. Both REMW and REMUW
+always sign-extend the 32-bit result to 64 bits, including on a divide by zero.
+"""
+
+[DIVUW]
+name = "Divide word unsigned"
+opcode = "OP-32 / DIVUW / MULDIV"
+encoding = "R"
+extension = "M"
+long_description = """
+DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of rs1 by the lower 32
+bits of rs2, treating them as signed and unsigned integers respectively, placing the 32-bit quotient
+in rd, sign-extended to 64 bits. REMW and REMUW are RV64 instructions that provide the
+corresponding signed and unsigned remainder operations respectively. Both REMW and REMUW
+always sign-extend the 32-bit result to 64 bits, including on a divide by zero.
+"""
+
+[REMW]
+name = "Remainder word"
+opcode = "OP-32 / REMW / MULDIV"
+encoding = "R"
+extension = "M"
+long_description = """
+DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of rs1 by the lower 32
+bits of rs2, treating them as signed and unsigned integers respectively, placing the 32-bit quotient
+in rd, sign-extended to 64 bits. REMW and REMUW are RV64 instructions that provide the
+corresponding signed and unsigned remainder operations respectively. Both REMW and REMUW
+always sign-extend the 32-bit result to 64 bits, including on a divide by zero.
+"""
+
+[REMUW]
+name = "Remainder word unsigned"
+opcode = "OP-32 / REMUW / MULDIV"
+encoding = "R"
+extension = "M"
+long_description = """
+DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of rs1 by the lower 32
+bits of rs2, treating them as signed and unsigned integers respectively, placing the 32-bit quotient
+in rd, sign-extended to 64 bits. REMW and REMUW are RV64 instructions that provide the
+corresponding signed and unsigned remainder operations respectively. Both REMW and REMUW
+always sign-extend the 32-bit result to 64 bits, including on a divide by zero.
+"""
+
+["LR.W"]
+name = "Load reserved word"
+opcode = "AMO / width / LR.W"
+encoding = "R"
+extension = "A"
+long_description = """
+Complex atomic memory operations on a single memory word or doubleword are performed with the
+load-reserved (LR) and store-conditional (SC) instructions. LR.W loads a word from the address
+in rs1, places the sign-extended value in rd, and registers a reservation set—a set of bytes that
+subsumes the bytes in the addressed word. SC.W conditionally writes a word in rs2 to the address
+in rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the
+bytes being written. If the SC.W succeeds, the instruction writes the word in rs2 to memory, and
+it writes zero to rd. If the SC.W fails, the instruction does not write to memory, and it writes a
+nonzero value to rd. Regardless of success or failure, executing an SC.W instruction invalidates
+any reservation held by this hart. LR.D and SC.D act analogously on doublewords and are only
+available on RV64. For RV64, LR.W and SC.W sign-extend the value placed in rd.
+"""
+
+["LR.D"]
+name = "Load reserved doubleword"
+opcode = "AMO / width / LR.D"
+encoding = "R"
+extension = "A"
+long_description = """
+Complex atomic memory operations on a single memory word or doubleword are performed with the
+load-reserved (LR) and store-conditional (SC) instructions. LR.W loads a word from the address
+in rs1, places the sign-extended value in rd, and registers a reservation set—a set of bytes that
+subsumes the bytes in the addressed word. SC.W conditionally writes a word in rs2 to the address
+in rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the
+bytes being written. If the SC.W succeeds, the instruction writes the word in rs2 to memory, and
+it writes zero to rd. If the SC.W fails, the instruction does not write to memory, and it writes a
+nonzero value to rd. Regardless of success or failure, executing an SC.W instruction invalidates
+any reservation held by this hart. LR.D and SC.D act analogously on doublewords and are only
+available on RV64. For RV64, LR.W and SC.W sign-extend the value placed in rd.
+"""
+
+["SC.W"]
+name = "Store conditional word"
+opcode = "AMO / width / SC.W"
+encoding = "R"
+extension = "A"
+long_description = """
+Complex atomic memory operations on a single memory word or doubleword are performed with the
+load-reserved (LR) and store-conditional (SC) instructions. LR.W loads a word from the address
+in rs1, places the sign-extended value in rd, and registers a reservation set—a set of bytes that
+subsumes the bytes in the addressed word. SC.W conditionally writes a word in rs2 to the address
+in rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the
+bytes being written. If the SC.W succeeds, the instruction writes the word in rs2 to memory, and
+it writes zero to rd. If the SC.W fails, the instruction does not write to memory, and it writes a
+nonzero value to rd. Regardless of success or failure, executing an SC.W instruction invalidates
+any reservation held by this hart. LR.D and SC.D act analogously on doublewords and are only
+available on RV64. For RV64, LR.W and SC.W sign-extend the value placed in rd.
+"""
+
+["SC.D"]
+name = "Store conditional doubleword"
+opcode = "AMO / width / SC.D"
+encoding = "R"
+extension = "A"
+long_description = """
+Complex atomic memory operations on a single memory word or doubleword are performed with the
+load-reserved (LR) and store-conditional (SC) instructions. LR.W loads a word from the address
+in rs1, places the sign-extended value in rd, and registers a reservation set—a set of bytes that
+subsumes the bytes in the addressed word. SC.W conditionally writes a word in rs2 to the address
+in rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the
+bytes being written. If the SC.W succeeds, the instruction writes the word in rs2 to memory, and
+it writes zero to rd. If the SC.W fails, the instruction does not write to memory, and it writes a
+nonzero value to rd. Regardless of success or failure, executing an SC.W instruction invalidates
+any reservation held by this hart. LR.D and SC.D act analogously on doublewords and are only
+available on RV64. For RV64, LR.W and SC.W sign-extend the value placed in rd.
+"""
+
+
+["AMOSWAP.W"]
+name = "Atomic swap word"
+opcode = "AMO / width / AMOSWAP.W"
+encoding = "R"
+extension = "A"
+long_description = """
+The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-
+tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-
+structions atomically load a data value from the address in rs1, place the value into register rd,
+apply a binary operator to the loaded value and the original value in rs2, then store the result back
+to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.
+For RV64, 32-bit AMOs always sign-extend the value placed in rd.
+
+The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and
+signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs
+can be used to implement parallel reduction operations, where typically the return value would be
+discarded by writing to x0.
+"""
+
+["AMOSWAP.D"]
+name = "Atomic swap doubleword"
+opcode = "AMO / width / AMOSWAP.D"
+encoding = "R"
+extension = "A"
+long_description = """
+The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-
+tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-
+structions atomically load a data value from the address in rs1, place the value into register rd,
+apply a binary operator to the loaded value and the original value in rs2, then store the result back
+to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.
+For RV64, 32-bit AMOs always sign-extend the value placed in rd.
+
+The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and
+signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs
+can be used to implement parallel reduction operations, where typically the return value would be
+discarded by writing to x0.
+"""
+
+
+["AMOADD.W"]
+name = "Atomic ADD word"
+opcode = "AMO / width / AMOADD.W"
+encoding = "R"
+extension = "A"
+long_description = """
+The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-
+tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-
+structions atomically load a data value from the address in rs1, place the value into register rd,
+apply a binary operator to the loaded value and the original value in rs2, then store the result back
+to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.
+For RV64, 32-bit AMOs always sign-extend the value placed in rd.
+
+The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and
+signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs
+can be used to implement parallel reduction operations, where typically the return value would be
+discarded by writing to x0.
+"""
+
+["AMOADD.D"]
+name = "Atomic ADD doubleword"
+opcode = "AMO / width / AMOADD.D"
+encoding = "R"
+extension = "A"
+long_description = """
+The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-
+tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-
+structions atomically load a data value from the address in rs1, place the value into register rd,
+apply a binary operator to the loaded value and the original value in rs2, then store the result back
+to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.
+For RV64, 32-bit AMOs always sign-extend the value placed in rd.
+
+The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and
+signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs
+can be used to implement parallel reduction operations, where typically the return value would be
+discarded by writing to x0.
+"""
+
+["AMOAND.W"]
+name = "Atomic AND word"
+opcode = "AMO / width / AMOAND.W"
+encoding = "R"
+extension = "A"
+long_description = """
+The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-
+tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-
+structions atomically load a data value from the address in rs1, place the value into register rd,
+apply a binary operator to the loaded value and the original value in rs2, then store the result back
+to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.
+For RV64, 32-bit AMOs always sign-extend the value placed in rd.
+
+The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and
+signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs
+can be used to implement parallel reduction operations, where typically the return value would be
+discarded by writing to x0.
+"""
+
+["AMOAND.D"]
+name = "Atomic AND doubleword"
+opcode = "AMO / width / AMOAND.D"
+encoding = "R"
+extension = "A"
+long_description = """
+The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-
+tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-
+structions atomically load a data value from the address in rs1, place the value into register rd,
+apply a binary operator to the loaded value and the original value in rs2, then store the result back
+to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.
+For RV64, 32-bit AMOs always sign-extend the value placed in rd.
+
+The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and
+signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs
+can be used to implement parallel reduction operations, where typically the return value would be
+discarded by writing to x0.
+"""
+
+["AMOOR.W"]
+name = "Atomic OR word"
+opcode = "AMO / width / AMOOR.W"
+encoding = "R"
+extension = "A"
+long_description = """
+The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-
+tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-
+structions atomically load a data value from the address in rs1, place the value into register rd,
+apply a binary operator to the loaded value and the original value in rs2, then store the result back
+to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.
+For RV64, 32-bit AMOs always sign-extend the value placed in rd.
+
+The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and
+signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs
+can be used to implement parallel reduction operations, where typically the return value would be
+discarded by writing to x0.
+"""
+
+["AMOOR.D"]
+name = "Atomic OR doubleword"
+opcode = "AMO / width / AMOOR.D"
+encoding = "R"
+extension = "A"
+long_description = """
+The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-
+tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-
+structions atomically load a data value from the address in rs1, place the value into register rd,
+apply a binary operator to the loaded value and the original value in rs2, then store the result back
+to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.
+For RV64, 32-bit AMOs always sign-extend the value placed in rd.
+
+The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and
+signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs
+can be used to implement parallel reduction operations, where typically the return value would be
+discarded by writing to x0.
+"""
+
+["AMOXOR.W"]
+name = "Atomic XOR word"
+opcode = "AMO / width / AMOXOR.W"
+encoding = "R"
+extension = "A"
+long_description = """
+The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-
+tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-
+structions atomically load a data value from the address in rs1, place the value into register rd,
+apply a binary operator to the loaded value and the original value in rs2, then store the result back
+to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.
+For RV64, 32-bit AMOs always sign-extend the value placed in rd.
+
+The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and
+signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs
+can be used to implement parallel reduction operations, where typically the return value would be
+discarded by writing to x0.
+"""
+
+["AMOXOR.D"]
+name = "Atomic XOR doubleword"
+opcode = "AMO / width / AMOXOR.D"
+encoding = "R"
+extension = "A"
+long_description = """
+The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-
+tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-
+structions atomically load a data value from the address in rs1, place the value into register rd,
+apply a binary operator to the loaded value and the original value in rs2, then store the result back
+to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.
+For RV64, 32-bit AMOs always sign-extend the value placed in rd.
+
+The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and
+signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs
+can be used to implement parallel reduction operations, where typically the return value would be
+discarded by writing to x0.
+"""
+
+["AMOMAX.W"]
+name = "Atomic MAX word"
+opcode = "AMO / width / AMOMAX.W"
+encoding = "R"
+extension = "A"
+long_description = """
+The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-
+tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-
+structions atomically load a data value from the address in rs1, place the value into register rd,
+apply a binary operator to the loaded value and the original value in rs2, then store the result back
+to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.
+For RV64, 32-bit AMOs always sign-extend the value placed in rd.
+
+The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and
+signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs
+can be used to implement parallel reduction operations, where typically the return value would be
+discarded by writing to x0.
+"""
+
+["AMOMAX.D"]
+name = "Atomic MAX doubleword"
+opcode = "AMO / width / AMOMAX.D"
+encoding = "R"
+extension = "A"
+long_description = """
+The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-
+tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-
+structions atomically load a data value from the address in rs1, place the value into register rd,
+apply a binary operator to the loaded value and the original value in rs2, then store the result back
+to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.
+For RV64, 32-bit AMOs always sign-extend the value placed in rd.
+
+The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and
+signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs
+can be used to implement parallel reduction operations, where typically the return value would be
+discarded by writing to x0.
+"""
+
+["AMOMAXU.W"]
+name = "Atomic MAXU word"
+opcode = "AMO / width / AMOMAXU.W"
+encoding = "R"
+extension = "A"
+long_description = """
+The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-
+tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-
+structions atomically load a data value from the address in rs1, place the value into register rd,
+apply a binary operator to the loaded value and the original value in rs2, then store the result back
+to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.
+For RV64, 32-bit AMOs always sign-extend the value placed in rd.
+
+The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and
+signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs
+can be used to implement parallel reduction operations, where typically the return value would be
+discarded by writing to x0.
+"""
+
+["AMOMAXU.D"]
+name = "Atomic MAXU doubleword"
+opcode = "AMO / width / AMOMAXU.D"
+encoding = "R"
+extension = "A"
+long_description = """
+The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-
+tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-
+structions atomically load a data value from the address in rs1, place the value into register rd,
+apply a binary operator to the loaded value and the original value in rs2, then store the result back
+to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.
+For RV64, 32-bit AMOs always sign-extend the value placed in rd.
+
+The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and
+signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs
+can be used to implement parallel reduction operations, where typically the return value would be
+discarded by writing to x0.
+"""
+
+["AMOMIN.W"]
+name = "Atomic MIN word"
+opcode = "AMO / width / AMOMIN.W"
+encoding = "R"
+extension = "A"
+long_description = """
+The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-
+tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-
+structions atomically load a data value from the address in rs1, place the value into register rd,
+apply a binary operator to the loaded value and the original value in rs2, then store the result back
+to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.
+For RV64, 32-bit AMOs always sign-extend the value placed in rd.
+
+The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and
+signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs
+can be used to implement parallel reduction operations, where typically the return value would be
+discarded by writing to x0.
+"""
+
+["AMOMIN.D"]
+name = "Atomic MIN doubleword"
+opcode = "AMO / width / AMOMIN.D"
+encoding = "R"
+extension = "A"
+long_description = """
+The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-
+tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-
+structions atomically load a data value from the address in rs1, place the value into register rd,
+apply a binary operator to the loaded value and the original value in rs2, then store the result back
+to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.
+For RV64, 32-bit AMOs always sign-extend the value placed in rd.
+
+The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and
+signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs
+can be used to implement parallel reduction operations, where typically the return value would be
+discarded by writing to x0.
+"""
+
+["AMOMINU.W"]
+name = "Atomic MINU word"
+opcode = "AMO / width / AMOMINU.W"
+encoding = "R"
+extension = "A"
+long_description = """
+The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-
+tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-
+structions atomically load a data value from the address in rs1, place the value into register rd,
+apply a binary operator to the loaded value and the original value in rs2, then store the result back
+to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.
+For RV64, 32-bit AMOs always sign-extend the value placed in rd.
+
+The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and
+signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs
+can be used to implement parallel reduction operations, where typically the return value would be
+discarded by writing to x0.
+"""
+
+["AMOMINU.D"]
+name = "Atomic MINU doubleword"
+opcode = "AMO / width / AMOMINU.D"
+encoding = "R"
+extension = "A"
+long_description = """
+The atomic memory operation (AMO) instructions perform read-modify-write operations for mul-
+tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in-
+structions atomically load a data value from the address in rs1, place the value into register rd,
+apply a binary operator to the loaded value and the original value in rs2, then store the result back
+to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory.
+For RV64, 32-bit AMOs always sign-extend the value placed in rd.
+
+The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and
+signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs
+can be used to implement parallel reduction operations, where typically the return value would be
+discarded by writing to x0.
+"""
+
+[FLW]
+name = "Floating point load word"
+opcode = "LOAD-FP"
+encoding = "I"
+extension = "F"
+long_description = """
+Floating-point loads and stores use the same base+offset addressing mode as the integer base ISA,
+with a base address in register rs1 and a 12-bit signed byte offset. The FLW instruction loads
+a single-precision floating-point value from memory into floating-point register rd. FSW stores a
+single-precision value from floating-point register rs2 to memory.
+"""
+
+[FSW]
+name = "Floating point store word"
+opcode = "STORE-FP"
+encoding = "I"
+extension = "F"
+long_description = """
+Floating-point loads and stores use the same base+offset addressing mode as the integer base ISA,
+with a base address in register rs1 and a 12-bit signed byte offset. The FLW instruction loads
+a single-precision floating-point value from memory into floating-point register rd. FSW stores a
+single-precision value from floating-point register rs2 to memory.
+"""
+
+[FADD]
+name = "Floating point add"
+opcode = "OP-FP / FADD"
+encoding = "R"
+extension = "F"
+long_description = """
+Floating-point arithmetic instructions with one or two source operands use the R-type format with
+the OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition
+68
+and multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating-
+point subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of
+rs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd.
+"""
+
+[FSUB]
+name = "Floating point subtract"
+opcode = "OP-FP / FSUB"
+encoding = "R"
+extension = "F"
+long_description = """
+Floating-point arithmetic instructions with one or two source operands use the R-type format with
+the OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition
+68
+and multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating-
+point subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of
+rs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd.
+"""
+
+
+[FMUL]
+name = "Floating point multiply"
+opcode = "OP-FP / FMUL"
+encoding = "R"
+extension = "F"
+long_description = """
+Floating-point arithmetic instructions with one or two source operands use the R-type format with
+the OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition
+68
+and multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating-
+point subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of
+rs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd.
+"""
+
+
+[FDIV]
+name = "Floating point divide"
+opcode = "OP-FP / FDIV"
+encoding = "R"
+extension = "F"
+long_description = """
+Floating-point arithmetic instructions with one or two source operands use the R-type format with
+the OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition
+68
+and multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating-
+point subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of
+rs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd.
+"""
+
+
+[FSQRT]
+name = "Floating point square root"
+opcode = "OP-FP / FSQRT"
+encoding = "R"
+extension = "F"
+long_description = """
+Floating-point arithmetic instructions with one or two source operands use the R-type format with
+the OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition
+68
+and multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating-
+point subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of
+rs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd.
+"""
+
+
+[FMIN]
+name = "Floating point min"
+opcode = "OP-FP / FMIN"
+encoding = "R"
+extension = "F"
+long_description = """
+Floating-point arithmetic instructions with one or two source operands use the R-type format with
+the OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition
+68
+and multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating-
+point subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of
+rs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd.
+"""
+
+
+[FMAX]
+name = "Floating point max"
+opcode = "OP-FP / F"
+encoding = "R"
+extension = "F"
+long_description = """
+Floating-point arithmetic instructions with one or two source operands use the R-type format with
+the OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition
+68
+and multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating-
+point subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of
+rs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd.
+"""
+
+
+[FMADD]
+name = "Floating point fused multiply-add"
+opcode = "FMADD"
+encoding = "R4"
+extension = "F"
+long_description = """
+Floating-point fused multiply-add instructions require a new standard instruction format. R4-type
+instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This
+format is only used by the floating-point fused multiply-add instructions.
+FMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to
+rd. FMADD.S computes (rs1×rs2)+rs3.
+FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result
+to rd. FMSUB.S computes (rs1×rs2)-rs3.
+FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and
+writes the final result to rd. FNMSUB.S computes -(rs1×rs2)+rs3.
+FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3,
+and writes the final result to rd. FNMADD.S computes -(rs1×rs2)-rs3.
+"""
+
+[FMSUB]
+name = "Floating point fused multiply-subtract"
+opcode = "FMSUB"
+encoding = "R4"
+extension = "F"
+long_description = """
+Floating-point fused multiply-add instructions require a new standard instruction format. R4-type
+instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This
+format is only used by the floating-point fused multiply-add instructions.
+FMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to
+rd. FMADD.S computes (rs1×rs2)+rs3.
+FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result
+to rd. FMSUB.S computes (rs1×rs2)-rs3.
+FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and
+writes the final result to rd. FNMSUB.S computes -(rs1×rs2)+rs3.
+FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3,
+and writes the final result to rd. FNMADD.S computes -(rs1×rs2)-rs3.
+"""
+
+[FNMADD]
+name = "Floating point fused negate multiply-add"
+opcode = "FNMADD"
+encoding = "R4"
+extension = "F"
+long_description = """
+Floating-point fused multiply-add instructions require a new standard instruction format. R4-type
+instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This
+format is only used by the floating-point fused multiply-add instructions.
+FMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to
+rd. FMADD.S computes (rs1×rs2)+rs3.
+FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result
+to rd. FMSUB.S computes (rs1×rs2)-rs3.
+FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and
+writes the final result to rd. FNMSUB.S computes -(rs1×rs2)+rs3.
+FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3,
+and writes the final result to rd. FNMADD.S computes -(rs1×rs2)-rs3.
+"""
+
+[FNMSUB]
+name = "Floating point fused negate multiply-subtract"
+opcode = "FMNSUB"
+encoding = "R4"
+extension = "F"
+long_description = """
+Floating-point fused multiply-add instructions require a new standard instruction format. R4-type
+instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This
+format is only used by the floating-point fused multiply-add instructions.
+FMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to
+rd. FMADD.S computes (rs1×rs2)+rs3.
+FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result
+to rd. FMSUB.S computes (rs1×rs2)-rs3.
+FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and
+writes the final result to rd. FNMSUB.S computes -(rs1×rs2)+rs3.
+FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3,
+and writes the final result to rd. FNMADD.S computes -(rs1×rs2)-rs3.
+"""
+
+
+
+["FCVT.W.S"]
+name = "Convert single floating point to word integer"
+opcode = "OP-FP / FCVT"
+encoding = "F"
+extension = "F"
+long_description = """
+Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the
+OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-
+point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W
+or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a
+floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and
+FCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S
+sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U]
+are RV64-only instructions. If the rounded result is not representable in the destination format, it
+is clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs
+for FCVT.int.S and the behavior for invalid inputs.
+
+All floating-point to integer and integer to floating-point conversion instructions round according
+to the rm field. A floating-point register can be initialized to floating-point positive zero using
+FCVT.S.W rd, x0, which will never set any exception flags.
+"""
+
+["FCVT.L.S"]
+name = "Convert single floating point to doubleword integer"
+opcode = "OP-FP / FCVT"
+encoding = "F"
+extension = "F"
+long_description = """
+Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the
+OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-
+point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W
+or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a
+floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and
+FCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S
+sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U]
+are RV64-only instructions. If the rounded result is not representable in the destination format, it
+is clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs
+for FCVT.int.S and the behavior for invalid inputs.
+
+All floating-point to integer and integer to floating-point conversion instructions round according
+to the rm field. A floating-point register can be initialized to floating-point positive zero using
+FCVT.S.W rd, x0, which will never set any exception flags.
+"""
+
+["FCVT.WU.S"]
+name = "Convert single floating point to unsigned word integer"
+opcode = "OP-FP / FCVT"
+encoding = "F"
+extension = "F"
+long_description = """
+Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the
+OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-
+point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W
+or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a
+floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and
+FCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S
+sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U]
+are RV64-only instructions. If the rounded result is not representable in the destination format, it
+is clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs
+for FCVT.int.S and the behavior for invalid inputs.
+
+All floating-point to integer and integer to floating-point conversion instructions round according
+to the rm field. A floating-point register can be initialized to floating-point positive zero using
+FCVT.S.W rd, x0, which will never set any exception flags.
+"""
+
+["FCVT.LU.S"]
+name = "Convert single floating point to unsigned doubleword integer"
+opcode = "OP-FP / FCVT"
+encoding = "F"
+extension = "F"
+long_description = """
+Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the
+OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-
+point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W
+or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a
+floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and
+FCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S
+sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U]
+are RV64-only instructions. If the rounded result is not representable in the destination format, it
+is clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs
+for FCVT.int.S and the behavior for invalid inputs.
+
+All floating-point to integer and integer to floating-point conversion instructions round according
+to the rm field. A floating-point register can be initialized to floating-point positive zero using
+FCVT.S.W rd, x0, which will never set any exception flags.
+"""
+
+
+
+["FCVT.S.W"]
+name = "Convert word integer to single floating point"
+opcode = "OP-FP / FCVT"
+encoding = "F"
+extension = "F"
+long_description = """
+Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the
+OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-
+point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W
+or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a
+floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and
+FCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S
+sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U]
+are RV64-only instructions. If the rounded result is not representable in the destination format, it
+is clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs
+for FCVT.int.S and the behavior for invalid inputs.
+
+All floating-point to integer and integer to floating-point conversion instructions round according
+to the rm field. A floating-point register can be initialized to floating-point positive zero using
+FCVT.S.W rd, x0, which will never set any exception flags.
+"""
+
+
+["FCVT.S.L"]
+name = "Convert double word integer to single floating point"
+opcode = "OP-FP / FCVT"
+encoding = "F"
+extension = "F"
+long_description = """
+Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the
+OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-
+point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W
+or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a
+floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and
+FCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S
+sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U]
+are RV64-only instructions. If the rounded result is not representable in the destination format, it
+is clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs
+for FCVT.int.S and the behavior for invalid inputs.
+
+All floating-point to integer and integer to floating-point conversion instructions round according
+to the rm field. A floating-point register can be initialized to floating-point positive zero using
+FCVT.S.W rd, x0, which will never set any exception flags.
+"""
+
+["FCVT.S.WU"]
+name = "Convert unsigned word integer to single floating point"
+opcode = "OP-FP / FCVT"
+encoding = "F"
+extension = "F"
+long_description = """
+Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the
+OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-
+point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W
+or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a
+floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and
+FCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S
+sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U]
+are RV64-only instructions. If the rounded result is not representable in the destination format, it
+is clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs
+for FCVT.int.S and the behavior for invalid inputs.
+
+All floating-point to integer and integer to floating-point conversion instructions round according
+to the rm field. A floating-point register can be initialized to floating-point positive zero using
+FCVT.S.W rd, x0, which will never set any exception flags.
+"""
+
+
+["FCVT.S.LU"]
+name = "Convert unsigned double word integer to single floating point"
+opcode = "OP-FP / FCVT"
+encoding = "F"
+extension = "F"
+long_description = """
+Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the
+OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-
+point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W
+or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a
+floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and
+FCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S
+sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U]
+are RV64-only instructions. If the rounded result is not representable in the destination format, it
+is clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs
+for FCVT.int.S and the behavior for invalid inputs.
+
+All floating-point to integer and integer to floating-point conversion instructions round according
+to the rm field. A floating-point register can be initialized to floating-point positive zero using
+FCVT.S.W rd, x0, which will never set any exception flags.
+"""
+
+["FSGNJ.S"]
+name = "Floating point sign injection"
+opcode = "OP-FP / FSGNJ"
+encoding = "R"
+extension = "F"
+long_description = """
+Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S,
+produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result’s sign bit is
+rs2’s sign bit; for FSGNJN, the result’s sign bit is the opposite of rs2’s sign bit; and for FSGNJX,
+the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set
+floating-point exception flags, nor do they canonicalize NaNs. Note, FSGNJ.S rx, ry, ry moves ry
+to rx (assembler pseudoinstruction FMV.S rx, ry); FSGNJN.S rx, ry, ry moves the negation of ry
+to rx (assembler pseudoinstruction FNEG.S rx, ry); and FSGNJX.S rx, ry, ry moves the absolute
+value of ry to rx (assembler pseudoinstruction FABS.S rx, ry).
+"""
+
+["FSGNJN.S"]
+name = "Floating point sign injection with negation"
+opcode = "OP-FP / FSGNJ"
+encoding = "R"
+extension = "F"
+long_description = """
+Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S,
+produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result’s sign bit is
+rs2’s sign bit; for FSGNJN, the result’s sign bit is the opposite of rs2’s sign bit; and for FSGNJX,
+the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set
+floating-point exception flags, nor do they canonicalize NaNs. Note, FSGNJ.S rx, ry, ry moves ry
+to rx (assembler pseudoinstruction FMV.S rx, ry); FSGNJN.S rx, ry, ry moves the negation of ry
+to rx (assembler pseudoinstruction FNEG.S rx, ry); and FSGNJX.S rx, ry, ry moves the absolute
+value of ry to rx (assembler pseudoinstruction FABS.S rx, ry).
+"""
+
+["FSGNJX.S"]
+name = "Floating point sign injection with SOR"
+opcode = "OP-FP / FSGNJ"
+encoding = "R"
+extension = "F"
+long_description = """
+Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S,
+produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result’s sign bit is
+rs2’s sign bit; for FSGNJN, the result’s sign bit is the opposite of rs2’s sign bit; and for FSGNJX,
+the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set
+floating-point exception flags, nor do they canonicalize NaNs. Note, FSGNJ.S rx, ry, ry moves ry
+to rx (assembler pseudoinstruction FMV.S rx, ry); FSGNJN.S rx, ry, ry moves the negation of ry
+to rx (assembler pseudoinstruction FNEG.S rx, ry); and FSGNJX.S rx, ry, ry moves the absolute
+value of ry to rx (assembler pseudoinstruction FABS.S rx, ry).
+"""
+
+["FMV.W.X"]
+name = "Move single floating point to integer register"
+opcode = "OP-FP / FMV.W.X"
+encoding = "R"
+extension = "F"
+long_description = """
+Instructions are provided to move bit patterns between the floating-point and integer registers.
+FMV.X.W moves the single-precision value in floating-point register rs1 represented in IEEE 754-
+2008 encoding to the lower 32 bits of integer register rd. The bits are not modified in the transfer,
+and in particular, the payloads of non-canonical NaNs are preserved. For RV64, the higher 32 bits
+of the destination register are filled with copies of the floating-point number’s sign bit.
+FMV.W.X moves the single-precision value encoded in IEEE 754-2008 standard encoding from the
+lower 32 bits of integer register rs1 to the floating-point register rd. The bits are not modified in
+the transfer, and in particular, the payloads of non-canonical NaNs are preserved.
+"""
+
+["FMV.X.W"]
+name = "Move word integer to single floating point register"
+opcode = "OP-FP / FMV.X.W"
+encoding = "R"
+extension = "F"
+long_description = """
+Instructions are provided to move bit patterns between the floating-point and integer registers.
+FMV.X.W moves the single-precision value in floating-point register rs1 represented in IEEE 754-
+2008 encoding to the lower 32 bits of integer register rd. The bits are not modified in the transfer,
+and in particular, the payloads of non-canonical NaNs are preserved. For RV64, the higher 32 bits
+of the destination register are filled with copies of the floating-point number’s sign bit.
+FMV.W.X moves the single-precision value encoded in IEEE 754-2008 standard encoding from the
+lower 32 bits of integer register rs1 to the floating-point register rd. The bits are not modified in
+the transfer, and in particular, the payloads of non-canonical NaNs are preserved.
+"""
+
+["FEQ.S"]
+name = "Floating point single precision equal"
+opcode = "OP-FP / EQ / FCMP"
+encoding = "R"
+extension = "F"
+long_description = """
+Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison be-
+tween floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd
+if the condition holds, and 0 otherwise.
+FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as signaling comparisons:
+that is, they set the invalid operation exception flag if either input is NaN. FEQ.S performs a quiet
+comparison: it only sets the invalid operation exception flag if either input is a signaling NaN. For
+all three instructions, the result is 0 if either operand is NaN.
+"""
+
+["FLT.S"]
+name = "Floating point single precision less than"
+opcode = "OP-FP / LT / FCMP"
+encoding = "R"
+extension = "F"
+long_description = """
+Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison be-
+tween floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd
+if the condition holds, and 0 otherwise.
+FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as signaling comparisons:
+that is, they set the invalid operation exception flag if either input is NaN. FEQ.S performs a quiet
+comparison: it only sets the invalid operation exception flag if either input is a signaling NaN. For
+all three instructions, the result is 0 if either operand is NaN.
+"""
+
+["FLE.S"]
+name = "Floating point single precision less than or equal"
+opcode = "OP-FP / LE / FCMP"
+encoding = "R"
+extension = "F"
+long_description = """
+Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison be-
+tween floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd
+if the condition holds, and 0 otherwise.
+FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as signaling comparisons:
+that is, they set the invalid operation exception flag if either input is NaN. FEQ.S performs a quiet
+comparison: it only sets the invalid operation exception flag if either input is a signaling NaN. For
+all three instructions, the result is 0 if either operand is NaN.
+"""
+
+["FCLASS.S"]
+name = "Floating point single precision classify"
+opcode = "OP-FP / FCLASS"
+encoding = "R"
+extension = "F"
+long_description = """
+The FCLASS.S instruction examines the value in floating-point register rs1 and writes to integer
+register rd a 10-bit mask that indicates the class of the floating-point number. The format of the
+mask is described in Table 11.5. The corresponding bit in rd will be set if the property is true
+and clear otherwise. All other bits in rd are cleared. Note that exactly one bit in rd will be set.
+FCLASS.S does not set the floating-point exception flags.
+"""
+
+["FMV.S"]
+name = "Copy single precision floating point register"
+opcode = ""
+encoding = "pseudo"
+extension = "F"
+long_description = """
+fsgnj.s rd, rs, rs
+"""
+
+["FABS.S"]
+name = "Single precision absolute value"
+opcode = ""
+encoding = "pseudo"
+extension = "F"
+long_description = """
+fsgnjx.s rd, rs, rs
+"""
+
+["FNEG.S"]
+name = "Single precision negate"
+opcode = ""
+encoding = "pseudo"
+extension = "F"
+long_description = """
+fsgnjn.s rd, rs, rs
+"""
+
+["FMV.D"]
+name = "Copy double precision floating point register"
+opcode = ""
+encoding = "pseudo"
+extension = "D"
+long_description = """
+fsgnj.d rd, rs, rs
+"""
+
+["FABS.D"]
+name = "Double precision absolute value"
+opcode = ""
+encoding = "pseudo"
+extension = "F"
+long_description = """
+fsgnjx.d rd, rs, rs
+"""
+
+["FNEG.D"]
+name = "Double precision negate"
+opcode = ""
+encoding = "pseudo"
+extension = "F"
+long_description = """
+fsgnjn.d rd, rs, rs
+"""
+
+#[]
+#name = ""
+#opcode = ""
+#encoding = ""
+#extension = ""
+#long_description = """
+#"""
+
+
diff --git a/tojson.py b/tojson.py
new file mode 100644
index 0000000..f1ac3f8
--- /dev/null
+++ b/tojson.py
@@ -0,0 +1,13 @@
+import toml
+import json
+
+data = toml.load(open("instructions.toml", "r"))
+
+newdata = []
+
+for op in data:
+    vals = data[op].copy()
+    vals["mnemonic"] = op
+    newdata.append(vals)
+
+json.dump(newdata, open("instructions.json", "w"))