swissChili | 9b3584b | 2021-02-18 13:57:27 -0800 | [diff] [blame] | 1 | #include "pic.h" |
swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame^] | 2 | #include "log.h" |
swissChili | 9b3584b | 2021-02-18 13:57:27 -0800 | [diff] [blame] | 3 | #include "io.h" |
| 4 | |
swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame^] | 5 | #define ICW1_ICW4 0x01 /* ICW4 (not) needed */ |
| 6 | #define ICW1_SINGLE 0x02 /* Single (cascade) mode */ |
| 7 | #define ICW1_INTERVAL4 0x04 /* Call address interval 4 (8) */ |
| 8 | #define ICW1_LEVEL 0x08 /* Level triggered (edge) mode */ |
| 9 | #define ICW1_INIT 0x10 /* Initialization - required! */ |
| 10 | |
| 11 | #define ICW4_8086 0x01 /* 8086/88 (MCS-80/85) mode */ |
| 12 | #define ICW4_AUTO 0x02 /* Auto (normal) EOI */ |
| 13 | #define ICW4_BUF_SLAVE 0x08 /* Buffered mode/slave */ |
| 14 | #define ICW4_BUF_MASTER 0x0C /* Buffered mode/master */ |
| 15 | #define ICW4_SFNM 0x10 /* Special fully nested (not) */ |
| 16 | |
| 17 | |
swissChili | 9b3584b | 2021-02-18 13:57:27 -0800 | [diff] [blame] | 18 | void (* interrupt_handlers[256])(struct registers); |
| 19 | |
| 20 | void pic_send_eoi(uchar interrupt) |
| 21 | { |
swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame^] | 22 | if (interrupt >= IRQ_TO_INT(8)) |
swissChili | 9b3584b | 2021-02-18 13:57:27 -0800 | [diff] [blame] | 23 | outb(PIC2_COMMAND, PIC_EOI); |
swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame^] | 24 | |
swissChili | 9b3584b | 2021-02-18 13:57:27 -0800 | [diff] [blame] | 25 | outb(PIC1_COMMAND, PIC_EOI); |
| 26 | } |
| 27 | |
| 28 | void irq_handler(struct registers regs) |
| 29 | { |
| 30 | pic_send_eoi(regs.interrupt_number); |
| 31 | |
swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame^] | 32 | kprintf("irq_handler called with interrupt %d\n", regs.interrupt_number); |
| 33 | |
swissChili | 9b3584b | 2021-02-18 13:57:27 -0800 | [diff] [blame] | 34 | if (interrupt_handlers[regs.interrupt_number]) |
| 35 | interrupt_handlers[regs.interrupt_number](regs); |
| 36 | } |
| 37 | |
| 38 | void add_interrupt_handler(uchar interrupt, void (* handler)(struct registers)) |
| 39 | { |
| 40 | interrupt_handlers[interrupt] = handler; |
| 41 | } |
swissChili | defeb0d | 2021-02-18 15:28:36 -0800 | [diff] [blame^] | 42 | |
| 43 | void pic_remap() |
| 44 | { |
| 45 | outb(0x20, 0x11); |
| 46 | outb(0xA0, 0x11); |
| 47 | outb(0x21, 0x20); |
| 48 | outb(0xA1, 0x28); |
| 49 | outb(0x21, 0x04); |
| 50 | outb(0xA1, 0x02); |
| 51 | outb(0x21, 0x01); |
| 52 | outb(0xA1, 0x01); |
| 53 | outb(0x21, 0x0); |
| 54 | outb(0xA1, 0x0); |
| 55 | |
| 56 | return; |
| 57 | } |