Add ESP32C3 RISC-V stub
diff --git a/src/kernel/riscv32/link.ld b/src/kernel/riscv32/link.ld
new file mode 100644
index 0000000..abbd617
--- /dev/null
+++ b/src/kernel/riscv32/link.ld
@@ -0,0 +1,46 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{
+ ram (rw) : ORIGIN = 0x80000000, LENGTH = 128M
+}
+
+PHDRS
+{
+ text PT_LOAD;
+ data PT_LOAD;
+ bss PT_LOAD;
+}
+
+SECTIONS
+{
+ .text : {
+ PROVIDE(_text_start = .);
+ *(.text.init) *(.text .text.*)
+ PROVIDE(_text_end = .);
+ } >ram AT>ram :text
+
+ .rodata : {
+ PROVIDE(_rodata_start = .);
+ *(.rodata .rodata.*)
+ PROVIDE(_rodata_end = .);
+ } >ram AT>ram :text
+
+ .data : {
+ . = ALIGN(4096);
+ PROVIDE(_data_start = .);
+ *(.sdata .sdata.*) *(.data .data.*)
+ PROVIDE(_data_end = .);
+ } >ram AT>ram :data
+
+ .bss :{
+ PROVIDE(_bss_start = .);
+ *(.sbss .sbss.*) *(.bss .bss.*)
+ PROVIDE(_bss_end = .);
+ } >ram AT>ram :bss
+
+ PROVIDE(_memory_start = ORIGIN(ram));
+ PROVIDE(_memory_end = ORIGIN(ram) + LENGTH(ram));
+}